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	ftp://ftp.cs.ucla.edu/pub/ficus/ucla_csd_910005.ps.gz, 19930607 Architecture of the Ficus Scalable Replicated File System Thomas W. Page, Jr. Richard G. Guy Gerald J. Popeky John S. Heidemann Department of Computer Science University of California Los Angeles Technical Report CSD-910005 March 1991
	ftp://ftp.cs.ucla.edu/pub/ficus/usenix_summer_91.ps.gz, 19930607 Management of Replicated Volume Location Data in the Ficus Replicated File System Thomas W. Page Jr., Richard G. Guy, John S. Heidemann, Gerald J. Popeky, Wai Mak, and Dieter Rothmeier Department of Computer Science University of California Los Angeles fpage,guy,popek,johnh,waimak,dieterg@cs.ucla.edu
	ftp://ftp.cs.ucla.edu/pub/ficus/usenix_summer_90.ps.gz, 19930607 Implementation of the Ficus Replicated File System Richard G. Guy, John S. Heidemann, Wai Mak, Thomas W. Page Jr., Gerald J. Popeky, and Dieter Rothmeier fguy,johnh,waimak,page,popek,dieterg@cs.ucla.edu Department of Computer Science University of California Los Angeles
	ftp://ftp.cs.ucla.edu/pub/ficus/ExpDistSys_90.ps.gz, 19930607 Name Transparency in Very Large Scale Distributed File Systems Richard G. Guy Thomas W. Page, Jr. John S. Heidemann Gerald J. Popeky Department of Computer Science University of California Los Angeles
	ftp://ftp.cs.ucla.edu/pub/ficus/proj_summary.ps.gz, 19930607 The Ficus Scalable File System Ficus Project Computer Science Department University of California Los Angeles June 11, 1991 Personnel Principal investigators Gerald Popek Thomas Page Research staff Richard Guy Dieter Rothmeier Wai Mak Students John Heidemann Yuguang Wu Contacts Dr. Thomas Page Dr.
	ftp://ftp.cs.ucla.edu/pub/ficus/WorkMgtReplData_92.ps.gz, 19930607 Primarily Disconnected Operation: Experiences with Ficus John S. Heidemann Thomas W. Page Richard G. Guy Gerald J. Popek Department of Computer Science University of California, Los Angeles
	ftp://ftp.cs.ucla.edu/pub/ficus/guy_dissertation.ps.gz, 19930607 Ficus: A Very Large Scale Reliable Distributed File System Richard G. Guy June 3, 1991 Technical Report CSD-910018 Computer Science Department University of California Los Angeles, CA 90024-1596 University of California Los Angeles Ficus: A Very Large Scale Reliable Distributed File System A
	ftp://ftp.cs.ucla.edu/pub/ficus/WorkMgtReplData_90.ps.gz, 19930607 Replication in Ficus Distributed File Systems Gerald J. Popeky Richard G. Guy Thomas W. Page, Jr. John S. Heidemann Department of Computer Science University of California Los Angeles
	ftp://ftp.cs.ucla.edu/pub/ficus/SympParallelDistributedProcessing_92.ps.gz, 19930607 is a power of two for LRU caches on multiprocessors. For page numbers between and 2k 1, instead of running stack evaluation on the same trace k+1 times for all the possible set lengths, one run of stack evaluation on the trace can give us the same hit ratio function for all set lengths. Since the most
	ftp://ftp.cs.ucla.edu/pub/ficus/ucla_csd_910056.ps.gz, 19930607 University of California Los Angeles Stackable Layers: An Architecture for File System Development A thesis submitted in partial satisfaction of the requirements for the degree Master of Science in Computer Science by John Shelby Heidemann 1991 This document is available as Technical Report CSD-910056
	ftp://ftp.cs.ucla.edu/pub/ficus/ucla_csd_930019.ps.gz, 19930707 To appear, ACM Transactions on Computer Systems. File System Development with Stackable Layers John S. Heidemann Gerald J. Popek Department of Computer Science University of California, Los Angeles Technical Report CSD-930019 July 1993
	ftp://ftp.cs.ucla.edu/pub/ficus/IntlConfNetworkProtocols_93.ps.gz, 19930804 Consistency Algorithms for Optimistic Replication R. G. Guy G. J. Popeky T. W. Page, Jr. Department of Computer Science University of California Los Angeles, CA 90024-1596
	ftp://ftp.cs.ucla.edu/pub/ficus/OLD_TECHREPORTS/ucla_csd_900044.ps.gz, 19930810 An Extensible, Stackable Interface for File System Development John S. Heidemann Gerald J. Popeky Department of Computer Science University of California, Los Angeles December 19, 1990
	ftp://ftp.cs.ucla.edu/pub/ficus/OLD_TECHREPORTS/ucla_csd_900009.ps.gz, 19930810 The Ficus Distributed File System: Replication via Stackable Layers Thomas W. Page, Jr. Gerald J. Popek Richard G. Guy John S. Heidemann Department of Computer Science University of California Los Angeles
	ftp://ftp.cs.ucla.edu/pub/ficus/WorkObjOrOpSys_90.ps.gz, 19930810 Stackable Layers: An Object-Oriented Approach to Distributed File System Architecture Thomas W. Page Jr., Gerald J. Popeky, Richard G. Guy Department of Computer Science University of California Los Angeles 1 Introduction Operating systems and their filing environments are traditionally implemented as
	ftp://ftp.cs.ucla.edu/pub/ficus/OLD_TECHREPORTS/ucla_csd_910007.ps.gz, 19930810 A Layered Approach to File System Development John S. Heidemann Gerald J. Popek Department of Computer Science University of California, Los Angeles Technical Report CSD-910007 March 1991
	ftp://ftp.cs.ucla.edu/pub/ficus/OLD_TECHREPORTS/ucla_csd_910006.ps.gz, 19930810 Algorithms for Consistency in Optimistically Replicated File Systems Richard G. Guy Gerald J. Popeky Department of Computer Science University of California Los Angeles Technical Report CSD-910006 March 1991
	ftp://ftp.cs.ucla.edu/tech-report/94-reports/940001/PartI23.ps, 19940201 17 Part I Representing Mechanical Devices There are three reasons for building computer representations of mechanical devices: (1) identify the types of structures used, so as to extend the types of inference that can be applied to device-related applications, (2) identify structures that globally
	ftp://ftp.cs.ucla.edu/tech-report/94-reports/940001/PartII67.ps, 19940201 231 PART II Reasoning About Mechanical Devices The overall goal of the FONM representation theory is to support the design and implementation of computational models of mechanical reasoning, particularly improvisation and invention. As a creative problem-solving task, invention can be viewed as an
	ftp://ftp.cs.ucla.edu/tech-report/94-reports/940001/PartI45.ps, 19940201 145 FAR SIDE copyright FARWORKS, INC. Reprinted with permission of UNIVERSAL PRESS SYNDICATE. All rights reserved. 146 147 Chapter 4 High-Level Dynamics and Device Function In this chapter, the representation constructs which are used in FONM to describe high-level device dynamics are presented. Every
	ftp://ftp.cs.ucla.edu/tech-report/94-reports/940001/PartIII8910.ps, 19940201 303 PART III Related Work, Scope, Extensions and Conclusions The value associated with the FONM representation theory is determined as a function of how it relates to existing work, how well it addresses the problems it is intended to address, and to what extent it provides new knowledge in a rapidly
	ftp://ftp.cs.ucla.edu/tech-report/94-reports/940001/AppGlossBib.ps, 19940201 355 Appendix Mechanical Device Representations This appendix is devoted to an in-depth presentation of the static, dynamic, and pragmatic representations for each of the devices that have been used in this research. Fig. A.1 illustrates the four mechanical device classes which are presented in this
	ftp://ftp.cs.ucla.edu/tech-report/94-reports/940003.ps.Z, 19940201 ffl-Transformation: Exploiting Phase Transitions to Solve Combinatorial Optimization Problems Weixiong Zhang and Joseph C. Pemberton Computer Science Department University of California, Los Angeles Los Angeles, CA 90024 Email: zhang@cs.ucla.edu, pemberto@cs.ucla.edu Phone: (310)206-3643 January 24,
	ftp://ftp.cs.ucla.edu/tech-report/94-reports/940005.ps.Z, 19940222 Synchronization Issues in Data-Parallel Languages Sundeep Prakash Maneesh Dhagat Rajive Bagrodia Computer Science Department University of California Los Angeles, CA 90024 February 10, 1994
	ftp://ftp.cs.ucla.edu/tech-report/94-reports/940007.ps.Z, 19940222 1 Genetic Design of Fuzzy Controllers Mark G. Cooper & Jacques J. Vidal University of California, Los Angeles 3531 Boelter Hall Los Angeles, California 90024 cooper@cs.ucla.edu vidal@cs.ucla.edu
	ftp://ftp.cs.ucla.edu/tech-report/94-reports/940008.ps.Z, 19940223 Genetic Design of Fuzzy Controllers: The Cart and Jointed-Pole Problem Mark G. Cooper & Jacques J. Vidal University of California, Los Angeles 4531 Boelter Hall Los Angeles, California 90024 cooper@cs.ucla.edu vidal@cs.ucla.edu This paper considers the application of genetic algorithms to the automatic
	ftp://ftp.cs.ucla.edu/tech-report/94-reports/940009cover.ps.Z, 19940304 Computer Science Department Technical Report University of California Los Angeles, CA 90024-1596 A FAULT TOLERANT DESIGN OF A MULTIMEDIA SERVER S. Berson February 1994 L. Golubchik CSD-940009 R. R. Muntz 1
	ftp://ftp.cs.ucla.edu/tech-report/94-reports/940009.ps.Z, 19940311 A Fault Tolerant Design of a Multimedia Server Steven Berson Leana Golubchik Richard R. Muntz UCLA Computer Science Department
	ftp://ftp.cs.ucla.edu/tech-report/94-reports/940012.ps.Z, 19940321 UC: A Set-Based Language for Data-Parallel Programming Rajive Bagrodia Mani Chandy+ Maneesh Dhagat *Computer Science Department, UCLA, Los Angeles, CA 90024 +Computer Science Department, Caltech, Pasadena, CA 91125
	ftp://ftp.cs.ucla.edu/tech-report/94-reports/940014.ps.Z, 19940323 Analysis of Striping Techniques in Robotic Storage Libraries Leana Golubchik 3436 Boelter Hall, Graduate Student Office UCLA Computer Science Department Los Angeles, CA 90024-1596 (310) 206-1803, leana@cs.ucla.edu Richard R. Muntz UCLA Computer Science Department Richard W. Watson Lawrence Livermore
	ftp://ftp.cs.ucla.edu/tech-report/94-reports/940013.ps.Z, 19940325 UNIVERSITY OF CALIFORNIA Los Angeles A SYNTHESIS SYSTEM FOR APPLICATION SPECIFIC ARRAYS IMPLEMENTING MATRIX COMPUTATIONS A dissertation submitted in partial satisfaction of the requirements for the degree of Doctor of Philosophy in Computer Science by James Jianhuang Liu 1994 1 Contents 1 Introduction 3
	ftp://ftp.cs.ucla.edu/tech-report/94-reports/940010.ps.Z, 19940325 Linear Sequential Arrays: Pipelining Arithmetic Data Paths Marianne E. Louie and Milo<=s D. Ercegovac Computer Science Department University of California, Los Angeles, CA 90024 March 3, 1994
	ftp://ftp.cs.ucla.edu/pub/ficus/ucla_csd_940017.ps.gz, 19940408 To appear, 1994 Summer Usenix Conference. Resolving File Conflicts in the Ficus File System Peter Reiher, John Heidemann, David Ratner, Greg Skinner, Gerald Popek Department of Computer Science University of California, Los Angeles Technical Report CSD-940017 April 1994
	ftp://ftp.cs.ucla.edu/pub/ficus/usenix_summer_94_resolver.ps.gz, 19940408 Resolving File Conflicts in the Ficus File System Peter Reiher, John Heidemann, David Ratner, Greg Skinner, Gerald Popek Department of Computer Science University of California, Los Angeles
	ftp://ftp.cs.ucla.edu/pub/ficus/usenix_summer_94_statistics.ps.gz, 19940408 An Analysis of Trace Data for Predictive File Caching in Mobile Computing Geoffrey H. Kuenning, Gerald J. Popek, Peter L. Reiher University of California, Los Angeles
	ftp://ftp.cs.ucla.edu/tech-report/94-reports/940004.ps.Z, 19940427 University of California Los Angeles Dual M-Sets : The Theoretical Framework and Applications A dissertation submitted in partial satisfaction of the requirements for the degree Doctor of Philosophy in Computer Science by Shen-Tzay Huang 1993 c Copyright by Shen-Tzay Huang 1993 The dissertation of
	ftp://ftp.cs.ucla.edu/pub/ficus/gds/www-as-env.ps, 19940509 The World Wide Web System as an Operating Environment Rawn Shah rawn@rtd.com RTD Systems & Networking, Inc. 2601 N Campbell Ave. Ste. 202B, Tucson, Arizona, 85719 USA, +1 602 318 0696 Introduction Its interesting to note the similarities between designs and projections of World Wide Web servers and
	ftp://ftp.cs.ucla.edu/tech-report/94-reports/940017.ps.Z, 19940531 To appear, 1994 Summer Usenix Conference. Resolving File Conflicts in the Ficus File System Peter Reiher, John Heidemann, David Ratner, Greg Skinner, Gerald Popek Department of Computer Science University of California, Los Angeles Technical Report CSD-940017 April 1994
	ftp://ftp.cs.ucla.edu/tech-report/94-reports/940015.ps.Z, 19940531 A General Methodology for Response and Delay Computations in VLSI Interconnects Andrew B. Kahng and Sudhakar Muddu UCLA Computer Science Department, Los Angeles, CA 90024-1596 USA abk@cs.ucla.edu, sudhakar@cs.ucla.edu
	ftp://ftp.cs.ucla.edu/tech-report/94-reports/940018.ps.Z, 19940531 A General Framework for Vertex Orderings, With Applications to Netlist Clustering C. J. Alpert and A. B. Kahng UCLA Computer Science Department, Los Angeles, CA 90024-1596
	ftp://ftp.cs.ucla.edu/tech-report/94-reports/940020.ps.Z, 19940531 Simultaneous Driver and Wire Sizing for Performance and Power Optimization Jason Cong and Cheng-Kok Koh Department of Computer Science University of California, Los Angeles, CA 90024
	ftp://ftp.cs.ucla.edu/tech-report/94-reports/940019.ps.Z, 19940531 When Clusters Meet Partitions: A New Density Objective for Circuit Decomposition J.-H. Dennis Huang and Andrew B. Kahng UCLA Computer Science Department, Los Angeles, CA 90024-1596 USA jenhsin@cs.ucla.edu, abk@cs.ucla.edu
	ftp://ftp.cs.ucla.edu/pub/ficus/ucla_csd_940016.ps.gz, 19940603 To appear, 1994 Summer Usenix Conference. An Analysis of Trace Data for Predictive File Caching in Mobile Computing Geoffrey H. Kuenning, Gerald J. Popek, Peter L. Reiher University of California, Los Angeles Technical Report CSD-940016 April 1994
	ftp://ftp.cs.ucla.edu/tech-report/94-reports/940021.ps.Z, 19940705 An Algorithm to Calculate Transient Distributions of Cumulative Reward Edmundo de Souza e Silva1 UCLA Computer Science Department Los Angeles, CA 90024 H. Richard Gail IBM Thomas J. Watson Research Center Yorktown Heights, NY 10598
	ftp://ftp.cs.ucla.edu/tech-report/94-reports/940023.ps.Z, 19940706 University of California Los Angeles Variable Precision Arithmetic with Lookup Table Based Field Programmable Gate Arrays A dissertation submitted in partial satisfaction of the requirements for the degree Doctor of Philosophy in Computer Science by Marianne Elise Louie 1994 c Copyright by Marianne
	ftp://ftp.cs.ucla.edu/pub/ficus/sysadmin.ps.gz, 19940801 Ficus Replicated File System: Installation and System Administrator's Guide The Ficus Project University of California Los Angeles July 12, 1994 Contents 1 Missing Sections 4 2 Roadmap to this Manual 4 3 Overview of Ficus 6 3.1 A Stackable Architecture : : : : : : : : : : : : : : : : : : : : : : : : 6
	ftp://ftp.cs.ucla.edu/pub/ficus/user.ps.gz, 19940801 Ficus Replicated File System: User's Guide Thomas Page University of California Los Angeles 1 Introduction to Ficus The Ficus filing layers allow users to store and access from one to several dozen replicas of their files. Copies may be located on the local machine, on other machines on the local area
	ftp://ftp.cs.ucla.edu/tech-report/94-reports/940026.ps.Z, 19940906 Simulated Annealing with Inaccurate Cost Functions DANIEL R. GREENING University of California, Los Angeles IBM T.J. Watson Research Center, Yorktown Heights, New York
	ftp://ftp.cs.ucla.edu/tech-report/94-reports/940028.ps.Z, 19940906 Efficient Solutions for a Class of Non-Markovian Models Edmundo de Souza e Silva1 UCLA Computer Science Department Los Angeles, CA 90024 H. Richard Gail IBM Thomas J. Watson Research Center Yorktown Heights, NY 10598 Richard R. Muntz1 UCLA Computer Science Department Los Angeles, CA 90024
	ftp://ftp.cs.ucla.edu/tech-report/94-reports/940030.ps.Z, 19940906 Integrating Task and Data Parallelism in UCy Maneesh Dhagat 6704A Boelter Hall, Computer Science Department, University of California at Los Angeles, Los Angeles, CA 90024 (310)825-4885 (phone) manu@cs.ucla.edu Rajive Bagrodia 4531E Boelter Hall, Computer Science Department, University of California at
	ftp://ftp.cs.ucla.edu/tech-report/94-reports/940024.ps.Z, 19940906 Towards a Modeling Framework for Geoscientific Data Eddie C. Sheky, Richard R. Muntz Data Mining Laboratory Computer Science Department University of California, Los Angeles, CA 90024 fshek, muntzg@cs.ucla.edu June 16, 1994
	ftp://ftp.cs.ucla.edu/tech-report/94-reports/940027.ps.Z, 19940906 Coordinated Checkpointing-Rollback Error Recovery for Distributed Shared Memory Multicomputers G. Janakiraman and Yuval Tamir Computer Science Department UCLA Los Angeles, California 90024
	ftp://ftp.cs.ucla.edu/tech-report/94-reports/940031/00.title.ps, 19940907 UNIVERSITY OF CALIFORNIA Los Angeles Crossbar Arbitration in Interconnection Networks for Multiprocessors and Multicomputers A dissertation submitted in partial satisfaction of the requirements for the degree Doctor of Philosophy in Computer Science by Hsin-Chou Chi 1994
	ftp://ftp.cs.ucla.edu/tech-report/94-reports/940031/2.prvwk.ps, 19940907 Chapter Two Previous Work In this chapter, research related to this work is surveyed. Section 2.1 describes several arbitration problems discovered in various applications. In many computer systems, resources (e.g. buses) are shared among users (e.g. processors). Conflicts occur when users compete for
	ftp://ftp.cs.ucla.edu/tech-report/94-reports/940031/6.appl.ps, 19940907 Chapter Six Arbiter Support for Adaptive Routing and for High-Priority Traffic This chapter describes the arbiter designs that support other types of traffic in the interconnection network. Arbiters for supporting adaptive routing and highpriority traffic are presented. Adaptive routing can be used to
	ftp://ftp.cs.ucla.edu/tech-report/94-reports/940031/1.intro.ps, 19940907 Chapter One Introduction The ability of multiprocessors and multicomputers to achieve high performance is dependent on interconnection networks that provide highbandwidth low-latency interprocessor communication. The key components of interconnection networks for large multiprocessors and multicomputers
	ftp://ftp.cs.ucla.edu/tech-report/94-reports/940031/5.stvprv.ps, 19940907 Chapter Five Starvation Prevention Multi-queue input buffers lead to high performance in multiprocessor interconnection networks by allowing packets at an input port to be processed in non-FIFO order. Symmetric crossbar arbiters efficiently resolve conflicting requests in switches with multi-queue input
	ftp://ftp.cs.ucla.edu/tech-report/94-reports/940031/3.sca.ps, 19940907 Chapter Three Symmetric Crossbar Arbiters Communication switches are basic components of interconnection networks for multiprocessors and multicomputers. The traffic through the switches is often delayed due to conflicting demands for resources, such as buffer space or output ports. Hence, switches must
	ftp://ftp.cs.ucla.edu/tech-report/94-reports/940031/04.toc.ps, 19940907 Table of Contents Chapter One - Introduction ........................................................................... 1 1.1. Crossbar Arbitration ............................................................................ 5 1.2. Organization of the Dissertation
	ftp://ftp.cs.ucla.edu/tech-report/94-reports/940031/01.copyright.ps, 19940907 Copyright by Hsin-Chou Chi 1994
	ftp://ftp.cs.ucla.edu/tech-report/94-reports/940031/08.vita_pub.ps, 19940907 VITA February 27, 1960 Born in Taichung, Taiwan 1982 B.S. Electrical Engineering National Taiwan University Taipei, Taiwan 1984 M.S. Electrical Engineering National Taiwan University Taipei, Taiwan 1984-1986 Instructor Chinese Army Signal School Chungli, Taiwan 1988-1993 Teaching Assistant, Teaching
	ftp://ftp.cs.ucla.edu/tech-report/94-reports/940031/09.abstract.ps, 19940907
	ftp://ftp.cs.ucla.edu/tech-report/94-reports/940031/4.dca.ps, 19940907 Chapter Four Decomposed Arbiters for Large Crossbars Crossbars are key components of communication switches used to construct multiprocessor interconnection networks. Small networks can be implemented as a single crossbar while large networks are composed of many small crossbars
	ftp://ftp.cs.ucla.edu/tech-report/94-reports/940031/05.tof.ps, 19940907 List of Figures 1.1 An Indirect Network for Multiprocessors ............................................. 2 1.2 A Direct Network for Multicomputers ................................................. 2 1.3 Organization of a Typical Communication Switch .............................. 3 1.4 A Switch with
	ftp://ftp.cs.ucla.edu/tech-report/94-reports/940031/7.summary.ps, 19940907 Chapter Seven Summary Significant improvements in the performance of communication switches can be achieved by using multi-queue input buffers instead of FIFO buffers. A crossbar is often used to connect multi-queue input buffers to the output ports of the switch and an arbiter is needed to resolve
	ftp://ftp.cs.ucla.edu/tech-report/94-reports/940036.ps.Z, 19941025 Spectral Partitioning: The More Eigenvectors, The Better Charles J. Alpert, So-Zen Yaoy UCLA Computer Science Department, Los Angeles, CA 90024-1596 y Cadence Design Sytems, San Jose, CA 94135
	ftp://ftp.cs.ucla.edu/tech-report/94-reports/940038.ps.Z, 19941025 F-G: A Fuzzy Algebra for Approximate Answering in Databases Berthier A.N. Ribeiro Richard Muntzy University of California, Los Angeles 1 Introduction: The Problem Conventional database systems deal with exact queries which specify constraints that have to be met precisely. For instance, if a user asks
	ftp://ftp.cs.ucla.edu/tech-report/94-reports/940037.ps.Z, 19941025 Reducing I/O Demand in Video-On-Demand Storage Servers Leana Golubchik John C.S. Luiy Richard Muntzz
	ftp://ftp.cs.ucla.edu/tech-report/94-reports/940041.ps.Z, 19941101 University of California Los Angeles Modeling, Simulation, and Control of Two-Legged Walking A dissertation submitted in partial satisfaction of the requirements for the degree Doctor of Philosophy in Computer Science by Alexis Paul Wieland 1994 c Copyright by Alexis Paul Wieland 1994 To my son
	ftp://ftp.cs.ucla.edu/tech-report/94-reports/940040.ps.Z, 19941101 Fault Tolerant Design of Multimedia Servers Steven Berson USC Information Sciences Institute Leana Golubchik UCLA Computer Science Department Richard R. Muntz UCLA Computer Science Department
	ftp://ftp.cs.ucla.edu/tech-report/94-reports/940039.ps.Z, 19941205 The Conquest Modeling Framework for Geoscientific Data Eddie C. Sheky, Richard R. Muntz Data Mining Laboratory Computer Science Department University of California, Los Angeles, CA 90024 fshek, muntzg@cs.ucla.edu November 1, 1994
	ftp://ftp.cs.ucla.edu/tech-report/94-reports/940042.ps.Z, 19941206 Design of a Scalable Multimedia Storage Manager Steven Berson, Ali Dashti, Martha Escobar-Molano, Shahram Ghandeharizadeh, Leana Golubchik, Richard Muntz, Cyrus Shahabi
	ftp://ftp.cs.ucla.edu/pub/ficus/mcsa94.ps.gz, 19950104 The Design of the Seer Predictive Caching System Geoffrey H. Kuenning Computer Science Department University of California, Los Angeles Los Angeles, CA 90024 geoff@ficus.cs.ucla.edu
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950004.ps.Z, 19950114 - 1 -
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950005.ps.Z, 19950209
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950006.ps.Z, 19950222 Investigation of Cardiac Cell Recovery Processes in Luo and Rudy Model Boris Y. Kogan, Simon D. Shpilfoygel February 21, 1995
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950008.ps.Z, 19950228 e ection routin can be use in networks whose stations ha e the same number o input an output links i e -len th packets arri e synchronously on the station s input links at the be innin o time slots, an each packet is route ia the output link that offers the shortest path to its estination Since the
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950010.ps.Z, 19950314 WAMISNOS Programmer s Guide 44 /* Print out Logical Link Control Statistics */ void llc_stat() int x; for (x=1;x
	ftp://ftp.cs.ucla.edu/tech-report/94-reports/940026X.ps.Z, 19950315 On the Bounded-Skew Clock and Steiner Routing Problems Dennis J.-H. Huang, Andrew B. Kahng and Chung-Wen Albert Tsao UCLA Computer Science Dept., Los Angeles, CA 90024-1596 USA
	ftp://ftp.cs.ucla.edu/pub/ficus/ratner_thesis.ps.gz, 19950320 University of California Los Angeles Selective Replication: Fine-Grain Control of Replicated Files A thesis submitted in partial satisfaction of the requirements for the degree Master of Science in Computer Science by David H. Ratner 1995 This document is available as Technical Report CSD-950007 of the
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950011/ch1.ps.Z, 19950323 Chapter One Introduction A computer program can be viewed as a set of instructions or operations which must be executed in order to complete a task. A primary goal of computer architecture is to design computers which will execute programs in the shortest time possible. Two possibilities for increasing
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950011/TOC.ps.Z, 19950323 Table of Contents Chapter One - Introduction ...................................................................... 1 1.1. Latency and Output Port Contention .............................................. 3 1.2. The Dynamically Allocated, Multi-Queue Buffer .......................... 6 1.3. The Scope of
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950011/ch6.ps.Z, 19950323 Chapter Six Buffer Performance Evaluation with Asynchronous Networks Chapter 4 presented an evaluation of the system-level performance of the DAMQ buffer. A Markov analysis and an event-driven simulator were used to measure the performance of the DAMQ buffer relative to other buffer architectures, in
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950007.ps.Z, 19950323 University of California Los Angeles Selective Replication: Fine-Grain Control of Replicated Files A thesis submitted in partial satisfaction of the requirements for the degree Master of Science in Computer Science by David H. Ratner 1995 This document is available as Technical Report CSD-950007 of the
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950011/1.cpt.ps.Z, 19950323 Copyright by Gregory Lee Frazier 1995
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950011/ch9.ps.Z, 19950323 Chapter Nine Summary and Conclusions The potential for large multiprocessors and multicomputers to achieve high performance can only be realized if they are provided with a high-throughput lowlatency communication network. Fast small n n switches are critical components for achieving high-speed
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950011/ch2.ps.Z, 19950323 Chapter Two Previous Work This chapter examines the work of previous researchers upon which our research is based. This dissertation examines buffer architectures and flow control mechanisms intended to support high throughput, low latency communication in scalable multicomputers. The current trend is
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950011/2.sig.ps.Z, 19950323 The dissertation of Gregory Lee Frazier is approved. hhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhh Kirby A. Baker hhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhh Henry Samueli hhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhh Milos D. Ercegovac hhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhh David Rennels
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950011/3.ded.ps.Z, 19950323 This dissertation is dedicated to Verra Morgan, the oil that keeps the wheels of the U.C.L.A. Computer Science Department turning, to my daughters, Mikaela and Joanna, whose love has redefined my world, and my wife, Tiffany, whose excellence sets the mark I try to match. iii
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950011/8.vit.ps.Z, 19950323 VITA February 15, 1964 Born in Ann Arbor, MI 1986 B.S. Computer Science and Engineering Massachusetts Institute of Technology Cambridge, MA 1986-1987 Chancellor's Fellow University of California Los Angeles, CA 1987-1990 Research Assistant, Research Associate University of California Los Angeles, CA
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950011/refs.ps.Z, 19950323 Bibliography A. Agarwal, B.-H. Lim, D. Kranz, and J. Kubiatowicz, ``APRIL: A Processor Architecture for Multiprocessing,'' Proceedings of the 17th Annual International Symposium on Computer Architecture, pp. 104-114 (May 1990). A. Agarwal, ``Limits on Interconnection Network
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950011/7.ack.ps.Z, 19950323 ACKNOWLEDGMENTS I must acknowledge the large number of people who helped make this dissertation a reality. Primary among them is my advisor, Professor Yuval Tamir, whose instruction and guidance were invaluable. Also important to my work was the advise and support of my cohorts in the UCLA VLSI Systems
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950011/TOF.ps.Z, 19950323 List of Figures 1.1 Switches in Multiprocessors and Multicomputers ........................... 2 1.2 Output Port Contention .................................................................... 4 1.3 The ComCoBB Chip ........................................................................ 6 3.1 Switch
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950011/9.abs.ps.Z, 19950323
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950011/ch4.ps.Z, 19950323 Chapter Four Buffer Performance Evaluation with Synchronous Networks This chapter presents evaluations of the performance of communication networks composed of switches implemented with the DAMQ buffer. The goal is to determine the performance characteristics of the DAMQ buffer and evaluate various
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950011/ch3.ps.Z, 19950323 Chapter Three The DAMQ Buffer Architecture When designing a switch, the goal is to enhance the performance of the communication network. A network's performance is measured by its saturation throughput and the average latency of packets traversing the network at a given throughput. Translating the
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950011/ch5.ps.Z, 19950323 Chapter Five Supporting High-Priority Traffic In Sec. 3.5, we discuss uses for the queues of a multiqueue buffer other than simply increasing the saturation throughput of the network or reducing the average latency. There are situations where one may desire ``especially good'' service for packets of a
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950011/ch7.ps.Z, 19950323 Chapter Seven The DAMQ Buffer Chip The previous three chapters of this dissertation evaluated the DAMQ buffer architecture in the context of a total communication network. This evaluation involved simulation studies that compared the performance of networks whose configurations are identical except for
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950011/TOT.ps.Z, 19950323 List of Tables 4.1 Results of Markov Analysis ............................................................. 51 4.2 Discarding Percentage vs. Throughput ............................................ 57 4.3 Latency vs. Throughput, Blocking Switches ................................... 59 4.4 Blocking
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950011/0.ttl.ps.Z, 19950323 UNIVERSITY OF CALIFORNIA Los Angeles Buffering and Flow Control in Communication Switches for Scalable Multicomputers A dissertation submitted in partial satisfaction of the requirements for the degree Doctor of Philosophy in Computer Science by Gregory Lee Frazier 1995
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950011/ch8.ps.Z, 19950323 Chapter Eight Flow Control This dissertation addresses the design of high performance communication switches for scalable multicomputers. Previous chapters focused on the buffer architecture as being a critical functional unit for such a design. This chapter focuses on flow control. Flow control is the
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950012/9.abstract.ps.Z, 19950328
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950012/7.acknowledgements.ps.Z, 19950328 ACKNOWLEDGMENTS I must acknowledge the large number of people who helped to make this dissertation a reality. First among them is my advisor, professor Yuval Tamir, from whom I learned an immense amount. His guidance has been invaluable. Also important to my work was the advice and support of my cohorts
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950012/1.copyright.ps.Z, 19950328 Copyright by Tiffany Michelle Frazier 1995
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950012/5.tof.ps.Z, 19950328 List of Figures 1.1 Inconsistent and Consistent Checkpoints ................................................ 5 1.2 The Domino Effect .................................................................................. 6 2.1 Inconsistent Post-Failure States
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950012/4.coord.ps.Z, 19950328 Chapter Four Coordinated Checkpointing Techniques Coordinated Checkpointing techniques checkpoint a set of processes together (the entire system or a subset thereof) in such a way that each pair of process states on stable storage are consistent with one another. The recovery algorithm is guaranteed to
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950012/3.msglog.ps.Z, 19950328 Chapter Three Message Logging Techniques Message logging techniques checkpoint process states and (log) interprocess messages onto stable storage. When a process fails and is rolled back, its message log is played back to it, so that when the message log has been depleted, the process is in a state
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950012/7.concl.ps.Z, 19950328 Chapter Seven Conclusions We have described several application-transparent error-recovery techniques which can be used to provide fault tolerance for large general-purpose multicomputers. Message logging techniques have the advantage of fast checkpoint and recovery sessions but may be inappropriate for
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950012/2.signature.ps.Z, 19950328 The dissertation of Tiffany Michelle Frazier is approved. hhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhh Kirby A. Baker hhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhh Richard Muntz hhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhh David A. Rennels hhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhh Algirdas A. Avizienis
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950012/4.toc.ps.Z, 19950328 Table of Contents Chapter One - Introduction ............................................................................ 1 1.1. Basic Concepts ........................................................................................ 4 1.2. Application-Specific Techniques
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950012/0.title.ps.Z, 19950328 UNIVERSITY OF CALIFORNIA Los Angeles Application-Transparent Error Recovery Techniques for Multicomputers A dissertation submitted in partial satisfaction of the requirements for the degree Doctor of Philosophy in Computer Science by Tiffany Michelle Frazier 1995
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950012/refs.ps.Z, 19950328 Bibliography M. Ahamad and L. Lin, ``Using Checkpoints to Localize the Effects of Faults in Distributed Systems,'' 8th Symposium on Reliable Distributed Systems, pp. 2-11 (October 1989). A. Avizienis, ``The N-Version Approach to Fault-Tolerant Software,'' IEEE Transactions on Software
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950012/8.vita_pub.ps.Z, 19950328 VITA November 23, 1964 Born in Ayer, Massachusetts 1981-1985 Edward and Hazel Felber Scholarship 1986 B.S. Computer Science University of Wisconsin-Madison Madison, Wisconsin 1986-1987 Teaching Assistant University of California, Los Angeles Los Angeles, California 1987-1989 Research Assistant
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950012/3.dedication.ps.Z, 19950328 To my husband, Greg. iii
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950012/6.perfeval.ps.Z, 19950328 Chapter Six Performance Evaluation In this chapter we characterize the overhead incurred when any checkpointing/rollback scheme is used to provide fault tolerance for a scalable multicomputer system similar to that which we describe in Chapter 2. We then characterize and compare the overhead incurred by
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950012/5.sim.ps.Z, 19950328 Chapter Five Execution-Driven Simulation of Error Recovery Techniques DERT (Distributed Error Recovery Testbed) is a testbed for simulating and evaluating the performance of several different classes of application-transparent distributed error recovery schemes. DERT is built on top of an event-driven,
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950012/2.sysmod.ps.Z, 19950328 Chapter Two System Model The target system for which error recovery is required is a multicomputer consisting of hundreds or thousands of VLSI nodes which communicate via messages over point-to-point links. In the first section of this chapter we describe the computational model of the target system.
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950012/6.tot.ps.Z, 19950328 List of Tables 1.1 Application-Transparent Error Recovery Techniques ............................. 19 5.1 Application Statistics ............................................................................... 162 5.2 Out-Of-Sync Problem
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950012/1.intro.ps.Z, 19950328 Chapter One Introduction Multicomputer systems, consisting of hundreds of processors interconnected by high-speed links, are now technologically and economically feasible. Such systems can achieve high performance for many applications at a low cost by exploiting parallelism. A
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950014.ps.Z, 19950330 A Simple Treatment of Property Preservation via Simulation Ching-Tsun Chou hchou@cs.ucla.edui Computer Science Department University of California at Los Angeles Los Angeles, CA 90024, U.S.A. (Last revised: 21 March 1995)
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950013.ps.Z, 19950330 Using Operational Intuition about Events and Causality in Assertional Proofs Ching-Tsun Chou hchou@cs.ucla.edui Computer Science Department, University of California at Los Angeles Los Angeles, CA 90024, U.S.A.
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950003.ps.Z, 19950403 Minimum-Cost Bounded-Skew Clock Routing Jason Cong and Cheng-Kok Koh UCLA Computer Science Department 310-206-2775 (tel) 310-825-2273 (fax) fcong,kohckg@cs.ucla.edu
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950001.ps.Z, 19950403 CONG AND HWANG UCLA CSD TR-950001 Simultaneous Depth and Area Minimization in LUT-based FPGA Mapping Jason Cong and Yean-Yow Hwang Department of Computer Science University of California, Los Angeles, CA 90024 January 31, 1995
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950002.ps.Z, 19950403 Performance Driven Routing with Multiple Sources Jason Cong Patrick H. Madden UCLA Computer Science Dept (310)206-2775, (310)UCLA-CSD Fax cong@cs.ucla.edu pickle@cs.ucla.edu March 31, 1995
	ftp://ftp.cs.ucla.edu/pub/ficus/psrg93.ps.gz, 19950404 TRUFFLES A SECURE SERVICE FOR WIDESPREAD FILE SHARING Peter Reiher Thomas Page, Jr. Gerald Popek UCLA Los Angeles, CA Jeff Cook Trusted Information Systems Los Angeles, CA Stephen Crocker Trusted Information Systems Glenwood, MD
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950009.ps.Z, 19950419 Page 1 Self-Organizing Networks relate Phonetic and Articulatory Speech Data Rik Crabbe Jacques J Vidal Georges Papcun
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950015.ps.Z, 19950427 1
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950016/4.MODEL.ps.Z, 19950505 Chapter Four Behavioral Modeling In order to verify that the AMPIRE design is architecturally correct, a behavioral model of the processor has been built with the Cadence Verilog hardware description language. Some selected modules and submodules have also been designed and simulated at the gate level
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950016/C.BIBLIO.ps.Z, 19950505 Bibliography C. G. Bell, A. Kotok, T. N. Hastings, and R. Hill, ``The Evolution of the DECsystem-10,'' in Computer Engineering, a DEC View of Hardware Systems Design (Bell, Mudge, and McNamara), Digital Press, Bedford, MA (1978). C. H. v. Berkel, ``Beware the Isochronic Fork,'' Nat.
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950016/A.VERILOG.ps.Z, 19950505 Appendix A Verilog Simulation Code The Verilog modules for AMPIRE are listed in alphabetical order, except for parameter and ampire.v , which appear first. iiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii Module Description iiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950016/2.PREV.ps.Z, 19950505 Chapter Two Previous Work 2.1. Handshake Protocols data req ack Figure 2.1: 2-Phase Handshake Protocol data req ack Figure 2.2: 4-Phase Handshake Protocol Whereas a synchronous system initiates a task cycle with clocks, an asynchronous system uses handshake signals to start and stop an activity. The
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950016/3.ARCH.ps.Z, 19950505 Chapter Three Processor Architecture 3.1. Instruction Set A subset of the DLX instruction set as presented in has been chosen for AMPIRE. The DLX RISC architecture is now widely studied in computer architecture classes, and it allows ease of implementation. Verilog models of DLX have been built
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950016/6.GATE.ps.Z, 19950505 Chapter Six Hardware Design and Gate-Level Simulation Gates.v in Appendix A is a collection of gate-level components, from which more complex circuits are built in other Verilog modules. The main purpose of this chapter is to show how some structures used in the behavioral Verilog model may be built in
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950016/7.END.ps.Z, 19950505 Chapter Seven Conclusion This thesis has demonstrated a fault-tolerance method for an asynchronous processor. The register reservation mechanism guarantees mutual exclusion on the registers and enables concurrency for independent instructions. The instruction log and delayed write buffers provide
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950016/5.SIMUL.ps.Z, 19950505 Chapter Five Behavioral Simulation 5.1. Instruction Fetch/Issue and Queue Operations In this chapter, several test programs and their simulation waveforms will be presented. Figures 5.1 and 5.2 show the effects of running the following program with slow and fast instruction memories, respectively.
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950016/1.INTRO.ps.Z, 19950505 Chapter One Introduction 1.1. Asynchronous Design Because of the advances in semiconductor technology, VLSI circuit density and speed have increased dramatically over the years. In a synchronous design, one of the limitations on system speed is clock skew, which is the phase difference of the clock
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950016/0.TITLE.ps.Z, 19950505 UNIVERSITY OF CALIFORNIA Los Angeles AMPIRE: Asynchronous Microprocessor with Instruction Retry A thesis submitted in partial satisfaction of the requirements for the degree Master of Science in Computer Science by Chia-Chi Chao 1995 Copyright by Chia-Chi Chao 1995 The thesis of Chia-Chi Chao is
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950016/B.ASM.ps.Z, 19950505 Appendix B AMPIRE Assembler B.1. Assembly Code Format The assembly code has the following format. Each part is optional and case- insensitive. The instruction set is shown in Table 3.1. Each register field is specified as R0 to R31. The immediate/offset field may be
	ftp://ftp.cs.ucla.edu/tech-report/94-reports/940016.ps.Z, 19950510 To appear, 1994 Summer Usenix Conference. An Analysis of Trace Data for Predictive File Caching in Mobile Computing Geoffrey H. Kuenning, Gerald J. Popek, Peter L. Reiher University of California, Los Angeles Technical Report CSD-940016 April 1994
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950017.ps.Z, 19950518 Just-in-time Scheduling for Video-on-Demand Storage Servers Steven Berson Richard R. Muntz UCLA Computer Science Department April 16, 1995
	ftp://ftp.cs.ucla.edu/tech-report/94-reports/940011.ps.Z, 19950519 Delay Analysis of VLSI Interconnections Using the Diffusion Equation Model Andrew B. Kahng and Sudhakar Muddu UCLA Computer Science Department, Los Angeles, CA 90024-1596 USA abk@cs.ucla.edu, sudhakar@cs.ucla.edu
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950018.ps.Z, 19950519 Cost Versus Distance In the Traveling Salesman Problem Kenneth D. Boese UCLA Computer Science Dept., Los Angeles, CA 90024-1596 USA
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950019.ps.Z, 19950519 A New Reflection-Based Approach for RC Interconnect Analysis Andrew B. Kahng and Sudhakar Muddu UCLA Computer Science Department, Los Angeles, CA 90024-1596 USA abk@cs.ucla.edu, sudhakar@cs.ucla.edu
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950020.ps.Z, 19950612 PARALLEL SWITCH-LEVEL SIMULATION of VLSI CIRCUITS Yu-an Chen, Vikas Jha, and Rajive Bagrodia Computer Science Department, University of California, Los Angeles, CA 90024 Computer Science Tech Report:950020, June 1995, UCLA
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950021.ps.Z, 19950629 Simulation Study of PRCA and FCVC in ATM LANs Supporting TCP/IP Mario Gerla, Carlos Pazos UCLA-Computer Science Departement Los Angeles, CA 90024 Vincenzo A. Signore Politecnico di Bari Italy
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950026.ps.Z, 19950811 Copyright c 1995 D. Stott Parker 13 References F. Chi o, M emoire sur les fonctions connues sous le nom de r esultantes ou de d eterminants". Turin, 32pp, 1853. (citation in ) J. Dongarra, I.S. Duff, D.C. Sorensen, H.A. van der Vorst, Solving Linear Systems on Vector and Shared Memory
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950028.ps.Z, 19950811 Quadtree Matrix Algorithms Revisited: Basic Issues and their Resolution D. Stott Parker Dinh Le stott@cs.ucla.edu dinh@cs.ucla.edu UCLA Computer Science Department Los Angeles, CA 90024-1596 USA With the quadtree representation of matrices popularized by Wise, many matrix algorithms are naturally
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950024.ps.Z, 19950811 Copyright c 1994, 1995 D. Stott Parker 20 D.S. Parker, Notes on Shuffle/Exchange-Type Switching Networks", IEEE Trans. Comput. C-29:3, 213-222 (March 1980). D.S. Parker, Explicit Formulas for the Results of Gaussian Elimination", Technical Report CSD-950025, UCLA Computer Science Department,
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950022.ps.Z, 19950811 Copyright c 1994, 1995 D. Stott Parker, Dinh L^e 14 J.H. Wilkinson, Error analysis of direct methods of matrix inversion", J. ACM 8, 28130, 1961. J.H. Wilkinson, Rounding Errors in Algebraic Processes, NJ: Prentice-Hall, Inc., 1963. David S. Wise, Matrix Algebra and Applicative
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950025.ps.Z, 19950811 Copyright c 1994, 1995 D. Stott Parker 19 N.J. Higham, D.J. Higham, Large Growth Factors in Gaussian Elimination with Pivoting", SIAM J. Matrix Anal. Appl. 10:3, 15564, April 1989. H. Hotelling, Some new methods in matrix inversion", Ann. Math. Stat. 14, 14, 1943. T. Muir, The
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950023.ps.Z, 19950811 Copyright c 1994, 1995 D. Stott Parker 20 G. Poole, L. Neal, Gaussian Elimination: When is Scaling Beneficial ", Linear Algebra Appl. 162, 30924, 1992. F.F. Rivera, R. Doallo, J.D. Bruguera, E.L. Zapata, R. Peskin, Gaussian Elimination with Pivoting on Hypercubes", Parallel Computing 14:1,
	ftp://ftp.cs.ucla.edu/pub/ficus/reiher/tw.papers/tw_temporal_decomp.ps.gz, 19950824 TEMPORAL DECOMPOSITION OF SIMULATIONS UNDER THE TIME WARP OPERATING SYSTEM Peter Reiher Jet Propulsion Laboratory Steven Bellenot Florida State University David Jefferson UCLA
	ftp://ftp.cs.ucla.edu/pub/ficus/reiher/tw.papers/tw_experience.ps.gz, 19950824 Experiences With Optimistic Synchronization For Distributed Operating Systems Peter L. Reiher Jet Propulsion Laboratory reiher@onyx.jpl.nasa.gov
	ftp://ftp.cs.ucla.edu/pub/ficus/reiher/tw.papers/tw_debug.ps.gz, 19950824 Debugging the Time Warp Operating System and Its Application Programs Peter L. Reiher Jet Propulsion Laboratory California Institute of Technology 4800 Oak Grove Drive Pasadena, CA 91109 reiher@onyx.jpl.nasa.gov Steven Bellenot The Florida State University Tallahassee, FL. 32306 bellenot@math.fsu.edu
	ftp://ftp.cs.ucla.edu/pub/ficus/reiher/tw.papers/tw_tutorial.ps.gz, 19950824 PARALLEL SIMULATION USING THE TIME WARP OPERATING SYSTEM Peter L. Reiher Jet Propulsion Laboratory 4800 Oak Grove Drive Pasadena, California 91109
	ftp://ftp.cs.ucla.edu/pub/ficus/reiher/tw.papers/tw_determ.ps.gz, 19950824 Providing Determinism In the Time Warp Operating System Costs, Benefits, and Implications Peter L. Reiher Frederick Wieland Philip Hontalas Jet Propulsion Laboratory 4800 Oak Grove Drive Pasadena, CA 91109
	ftp://ftp.cs.ucla.edu/pub/ficus/reiher/tw.papers/dlm.ps.gz, 19950825 VIRTUAL TIME BASED DYNAMIC LOAD MANAGEMENT IN THE TIME WARP OPERATING SYSTEM Peter L. Reiher Jet Propulsion Laboratory 4800 Oak Grove Drive Pasadena, CA 91109-8099 David Jefferson Department of Computer Science University of California, Los Angeles Los Angeles, CA 90024 Keywords: Time Warp, dynamic load
	ftp://ftp.cs.ucla.edu/pub/ficus/reiher/tw.papers/shark.ps.gz, 19950825 A TIME WARP IMPLEMENTATION OF SHARKS WORLD Matthew T. Presley Peter L. Reiher Jet Propulsion Laboratory 4800 Oak Grove Drive Pasadena, California 91109 Steven Bellenot Department of Mathematics The Florida State University Tallahassee, Florida 32306
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950030.ps.Z, 19950830 Bounded-Skew Clock and Steiner Routing Under Elmore Delay Jason Cong, Andrew B. Kahng, Cheng-Kok Koh and C.-W. Albert Tsao Department of Computer Science University of California, Los Angeles, CA 90024
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950029.ps.Z, 19950912 Improved Limited Discrepancy Search Richard E. Korf Computer Science Department University of California, Los Angeles Los Angeles, Ca. 90024 korf@cs.ucla.edu July 26, 1995
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950033.ps.Z, 19950912 Defining and Measuring Conflicts in Optimistic Replication John Heidemann Ashvin Goel Gerald Popek University of California, Los Angeles Technical report UCLA-CSD-950033
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950034.ps.Z, 19950914 Accurate Analytical Delay Models for VLSI Interconnects Andrew B. Kahng and Sudhakar Muddu UCLA Computer Science Department, Los Angeles, CA 90024-1596 USA abk@cs.ucla.edu, sudhakar@cs.ucla.edu
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950035.ps.Z, 19950915 Improved Large-Step Markov Chain Variants for the Symmetric TSP Inki Hong, Andrew B. Kahng and Byung-Ro Moon UCLA Computer Science Department Los Angeles, CA 90095-1596 USA September 14, 1995
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950027.ps.Z, 19951030 Schur Complements obey Lambek's Categorial Grammar: another view of Gaussian Elimination and LU Decomposition D. Stott Parker stott@cs.ucla.edu Computer Science Department University of California Los Angeles, CA 90024-1596 October 20, 1995
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950037.ps.Z, 19951206 The randomizing FFT: an alternative to pivoting in Gaussian elimination D. Stott Parker Brad Pierce stott@cs.ucla.edu pierce@cs.ucla.edu Computer Science Department University of California Los Angeles, CA 90024-1596
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950063.ps.Z, 19960105 A block matrix generalization of Gauss-Jordan elimination using Haynsworth's quotient formula for Schur complements Brad Pierce D. Stott Parker pierce@cs.ucla.edu stott@cs.ucla.edu Computer Science Department University of California Los Angeles, CA 90095-1596
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950058.ps.Z, 19960105 1 of 32 Multiple Constant Multiplications: Efficient and Versatile Framework and Algorithms for Exploring Common Subexpression Elimination Miodrag Potkonjak Department of Computer Science, University of California, Los Angeles, CA 90024 Mani B. Srivastava AT&T Bell Laboratories, Murray Hill, NJ 07974
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950053.ps.Z, 19960105 1 of 33 Hot Potato Techniques in High Level Synthesis Miodrag Potkonjak Sujit Dey C&C Research Laboratories, NEC USA, 4 Independence Way, Princeton, NJ 08540
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950047.ps.Z, 19960105 On Heterogeneous Distributed Geoscientific Query Processing Eddie C. Shekyz, Edmond Mesrobiany, and Richard R. Muntzy Computer Science Departmenty Information Sciences Laboratoryz University of California Hughes Research Laboratories Los Angeles, CA 90024 Malibu, CA 90265
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950056.ps.Z, 19960105 Power Optimization in Programmable Processors and ASIC Implementations of Linear Systems: Transformation-based Approach
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950066.ps.Z, 19960105 Analysis of the Bidirectional Shufflenet ..." Leonardi et al. 19 (one forward hop followed by a backward hop followed by another forward hop) exists. We proved earlier that this is not optimal. If the central sequence is longer than 1 hop but not greater than the other two sequences, there must be at
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950060.ps.Z, 19960105 Algorithm Selection using Behavioral Synthesis Miodrag Potkonjak Dept. of Computer Science, University of California, Los Angeles Jan Rabaey Dept. of EECS, University of California, Berkeley HYPER is a third generation high level synthesis system, targeted at numerically intensive applications. By
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950057.ps.Z, 19960105 Behavioral Optimization using the Manipulation of Timing Constraints Miodrag Potkonjak Department of Computer Science, University of California, Los Angeles, CA 90024 Mani B. Srivastava AT&T Bell Laboratories, Murray Hill, NJ 07974
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950054.ps.Z, 19960105 System-Level Design Guidance Using Structural Algorithmic Properties Lisa Guerra EECS Department University of California, Berkeley, CA 94720 Miodrag Potkonjak C&CCS Department University of California, Los Angeles, CA 90024 Jan Rabaey EECS Department University of California, Berkeley, CA 94720
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950064.ps.Z, 19960105 Deadlock-Free Routing in an Optical Interconnect for High-Speed Wormhole Routing Networks Prasasth Palnati , Mario Gerlay 405 Hilgard Ave, Computer Science Department, University of California, Los Angeles, CA 90024 fpalnati,gerlag@cs.ucla.edu Ph: (310) 825-1888 Emilio Leonardi Department of Electronics
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950045.ps.Z, 19960105 Structural Gate Decomposition for Depth-Optimal Technology Mapping in LUT-based FPGA Jason Cong and Yean-Yow Hwang Department of Computer Science University of California, Los Angeles Los Angeles, CA 90024
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950065.ps.Z, 19960105 Congestion Control Techniques in Wormhole Networks, by Palnati et al. 22 P. Palnati, M. Gerla, and E. Leonardi. Deadlock-free Routing in a Hierarchical Supercomputer Interconnection Network. Submitted for publication. P. Palnati, E. Leonardi, and M. Gerla. Performance Analysis of Bidirectional
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950061.ps.Z, 19960105 Techniques for Implementation of At-Speed Testable, High Performance, and Low Cost Linear Designs Miodrag Potkonjak Sujit Dey Kevin T. Kornegay CS Department C&C Research Labs Department of ECE University of California NEC USA Purdue University Los Angeles, CA Princeton, NJ West Lafayete, IN
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950052.ps.Z, 19960105 Optimum and Heuristic Transformation Techniques for Simultaneous Optimization of Latency and Throughput Mani B. Srivastava AT&T Bell Laboratories 600 Mountain Avenue Murray Hill, NJ 07974 and Miodrag Potkonjak Department of Computer Science University of California Los Angeles, CA 90024 Optimum and
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950059.ps.Z, 19960105 AT VLSI High Level Synthesis Laws: Theory and Practice 1 of 21 AT VLSI High Level Synthesis Laws: Theory and Practice Miodrag Potkonjak Computer Science Department University of California Los, Angeles, Ca 90024 Jan Rabaey University of California at Berkeley Dept. of EECS Berkeley, CA 94720
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950055.ps.Z, 19960105 Design-For-Debugging of Application Specific Designs
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950046.ps.Z, 19960109 Simultaneous Transistor and Interconnect Sizing Using General Dominance Property Jason Cong and Lei He Department of Computer Science University of California, Los Angeles, CA 90095
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950062.ps.Z, 19960109 Optimal Number Partitioning Richard E. Korf Computer Science Department University of California, Los Angeles Los Angeles, Ca. 90024 korf@cs.ucla.edu August 18, 1995
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950044.ps.Z, 19960109 A Formal Semantics for Composite Temporal Events in Active Database Rules Iakovos Motakis Carlo Zaniolo Computer Science Department, University of California Los Angeles, California 90024 motakis@cs.ucla.edu zaniolo@cs.ucla.edu
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950049.ps.Z, 19960110 Cooperative Mobile Robotics: Antecedents and Directions Y. Uny Cao, Alex S. Fukunaga, and Andrew B. Kahng UCLA Computer Science Department, Los Angeles, CA 90024-1596
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950067.ps.Z, 19960110 Improving the Performance of Evolutionary Optimization by Dynamically Scaling the Evaluation Function Alex S. Fukunaga and Andrew B. Kahng Computer Science Department University of California, Los Angeles Los Angeles, CA 90095-1596, USA ffukunaga,abkg@cs.ucla.edu
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950048.ps.Z, 19960110 A year's worth (sampled twice a day) of sea level pressure data (single precision floating point) generated by UCLA AGCM model with a 4ffi Latitude by 5ffi Longitude grid cell resolution is 9250560 bytes (730x44x72x4). Each grid slice" is therefore 12672 bytes. In this example, the dataset was stored
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950043.ps.Z, 19960112 A Graphical Solution to Statistical Adjustment Judea Pearl Cognitive Systems Laboratory Computer Science Department University of California, Los Angeles, CA 90024 judea@cs.ucla.edu
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950041.ps.Z, 19960112 Axiomatic Characterization of Directed Graphs Azaria Paz Judea Pearl Cognitive Systems Laboratory Computer Science Department University of California, Los Angeles, CA 90024 judea@cs.ucla.edu
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950050.ps.Z, 19960112 A Theory on Partially-Dependent Functional Decomposition with Application in LUT-based FPGA Jason Cong and Yean-Yow Hwang Department of Computer Science University of California, Los Angeles Los Angeles, CA 90024
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950031.ps.Z, 19960116 Optimal Wiresizing for Interconnects with Multiple Sources Jason Cong and Lei He Department of Computer Science University of California, Los Angeles, CA 90095 cong@cs.ucla.edu helei@cs.ucla.edu
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950036.ps.Z, 19960116 1 Interactive Explanation for Cooperative Information Systems Michael J.Minock Wesley W. Chu minock@cs.ucla.edu wwc@cs.ucla.edu Computer Science Department, University of California at Los Angeles Cooperative Information Systems let users pose imprecise queries and receive approximate or summary answers
	ftp://ftp.cs.ucla.edu/tech-report/96-reports/960002.ps.Z, 19960123 A Hybrid Multilevel/Genetic Approach for Circuit Partitioning Charles J. Alpert, Lars W. Hageny, and Andrew B. Kahng UCLA Computer Science Department, Los Angeles, CA 90095-1596 y Cadence Design Systems, San Jose, CA 94135
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950051.ps.Z, 19960123 Efficient Gate Delay Modeling for Large Interconnect Loads Andrew B. Kahng and Sudhakar Muddu UCLA Computer Science Department, Los Angeles, CA 90095-1596 USA abk@cs.ucla.edu, sudhakar@cs.ucla.edu
	ftp://ftp.cs.ucla.edu/tech-report/96-reports/960003.ps.Z, 19960307 Greed and Majorization (ABSTRACT) D.Stott Parker Prasad Ram Computer Science Department University of California Los Angeles, CA 90024-1596 November 29, 1994
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950038.ps.Z, 19960311 Input randomization and automatic derivation of systolic arrays for matrix computations Dinh L^e D. Stott Parker Brad Pierce Computer Science Department, UCLA School of Engineering and Applied Science Los Angeles, CA 90095-1596, USA
	ftp://ftp.cs.ucla.edu/tech-report/96-reports/960004.ps.Z, 19960319 Max-Min Rate Control Algorithm for Available Bit Rate Service in ATM Networks Sudhakar Muddu UCLA Computer Science Department Los Angeles, CA 90095-1596 sudhakar@cs.ucla.edu Christos Tryfonas , Fabio M. Chiussi, and Vijay P. Kumar AT&T Bell Laboratories ATM Networks Research Department 101 Crawfords
	ftp://ftp.cs.ucla.edu/tech-report/96-reports/960005.ps.Z, 19960319 1 Behavioral-Level Synthesis of Heterogeneous BISR Reconfigurable ASICs1 Lisa Guerra , Miodrag Potkonjak , and Jan Rabaey University of California - Berkeley, EECS Department, Berkeley, CA 94720 University of California - Los Angeles, CS Department, Los Angeles, CA 90095 Keywords: Behavioral-Level
	ftp://ftp.cs.ucla.edu/tech-report/96-reports/960007.ps.Z, 19960319 Algorithm Selection: A Quantitative Optimization-Intensive Approach 1 Miodrag Potkonjak Dept. of Computer Science, University of California, Los Angeles, CA 90095 Jan Rabaey Dept. of EECS, University of California, Berkeley, CA 94720
	ftp://ftp.cs.ucla.edu/tech-report/96-reports/960008.ps.Z, 19960319 Maximally Fast and Arbitrarily Fast Hardware Efficient Implementation of Linear and Feedback Linear Computations 1 Miodrag Potkonjak Dept. of Computer Science, University of California, Los Angeles, CA 90095 Jan M. Rabaey Dept. of EECS, University of California, Berkeley, CA 94720 Keywords: digital
	ftp://ftp.cs.ucla.edu/tech-report/96-reports/960009.ps.Z, 19960319 Optimizing Systems for Effective Block-Processing: The k-Delay Problem Kumar N. Lalgudi Marios C. Papaefthymiou Department of Electrical Engineering Yale University New Haven, CT 06520 Miodrag Potkonjak Department of Computer Science University of California Los Angeles, CA 90095 February 12, 1996
	ftp://ftp.cs.ucla.edu/tech-report/96-reports/960010.ps.Z, 19960401 Multicasting Protocols for High-Speed, Wormhole-Routing Local Area Networks Mario Gerla, Prasasth Palnati, Simon Walton
	ftp://ftp.cs.ucla.edu/tech-report/96-reports/960011.ps.Z, 19960402 University of California Los Angeles View Consistency for Optimistic Replication A thesis submitted in partial satisfaction of the requirements for the degree Master of Science in Computer Science by Ashvin Goel 1996 c Copyright by Ashvin Goel 1996 The thesis of Ashvin Goel is approved. Mario Gerla
	ftp://ftp.cs.ucla.edu/tech-report/96-reports/960014.ps.Z, 19960406 Quality of Service Support in High-Speed, Wormhole Routing Networks Mario Gerla, B. Kannan, Bruce Kwan, Prasasth Palnati, Simon Walton UCLA, 405 Hilgard Ave, Los Angeles, CA 90095-1596 Emilio Leonardi, Fabio Neri Dipartimento di Elettronica Politecnico di Torino, Torino, Italy 10129 Phone: (310) 825
	ftp://ftp.cs.ucla.edu/tech-report/96-reports/960013.ps.Z, 19960422 Analysis of RC Interconnections Under Ramp Input Andrew B. Kahng and Sudhakar Muddu UCLA Computer Science Department, Los Angeles, CA 90095-1596 USA abk@cs.ucla.edu, sudhakar@cs.ucla.edu
	ftp://ftp.cs.ucla.edu/tech-report/96-reports/960015.ps.Z, 19960430 Analytical Delay Models for VLSI Interconnects Under Ramp Input Andrew B. Kahng, Kei Masuko, and Sudhakar Muddu UCLA Computer Science Department, Los Angeles, CA 90095-1596 USA abk@cs.ucla.edu, masuko@cs.ucla.edu, sudhakar@cs.ucla.edu
	ftp://ftp.cs.ucla.edu/tech-report/95-reports/950032.2.ps.Z, 19960528 Stackable Design of File Systems John Shelby Heidemann University of California, Los Angeles September, 1995 A dissertation submitted in partial satisfaction of the requirements for the degree Doctor of Philosophy in Computer Science UCLA Computer Science Department Technical Report UCLA-CSD-950032
	ftp://ftp.cs.ucla.edu/tech-report/96-reports/960016.ps.Z, 19960612 Efficient Analyses and Models of VLSI and MCM Interconnects Andrew B. Kahng and Sudhakar Muddu UCLA Computer Science Department, Los Angeles, CA 90024-1596 abk@cs.ucla.edu, sudhakar@cs.ucla.edu
	ftp://ftp.cs.ucla.edu/tech-report/96-reports/960017.ps.Z, 19960620 Simultaneous Buffer and Wire Sizing for Performance and Power Optimization Jason Cong, Cheng-Kok Koh Kwok-Shing Leung fcong, kohckg@cs.ucla.edu ksleung@ichips.intel.com Computer Science Dept., UCLA Intel Corporation
	ftp://ftp.cs.ucla.edu/tech-report/96-reports/960019.ps.Z, 19960710 Three-Processor Tasks Are Undecidable Eli Gafni eli@cs.ucla.edu Elias Koutsoupias elias@cs.ucla.edu
	ftp://ftp.cs.ucla.edu/tech-report/96-reports/960025.ps.Z, 19960711 Power Optimization in Disk-Based Real-Time Application Specific Systems Inki Hong and Miodrag Potkonjak Computer Science Dept., University of California, Los Angeles, CA
	ftp://ftp.cs.ucla.edu/tech-report/96-reports/960022.ps.Z, 19960711 1 of 12 Throughput Optimization in Disk-Based Real-Time Application Specific Systems Stephen Docy, Inki Hong, and Miodrag Potkonjak Computer Science Dept., University of California, Los Angeles, CA
	ftp://ftp.cs.ucla.edu/tech-report/96-reports/960021.ps.Z, 19960711 23 of 23 1994. J. Soukup, Circuits Layout , Proc. of the IEEE, Vol. 69, No. 10, pp. 1281-1304, October 1981. J.A. Stankovic, M. Spuri, M. Di Natale, G.C. Buttazzo, Implications of Classical Scheduling Results for Real-Time Systems , IEEE Computer, Vol. 28, No. 6, pp. 16-25, June 1995.
	ftp://ftp.cs.ucla.edu/tech-report/96-reports/960023.ps.Z, 19960711 HETEROGENEOUS BUILT-IN RESILIENCY OF APPLICATION SPECIFIC PROGRAMMABLE PROCESSORS
	ftp://ftp.cs.ucla.edu/tech-report/96-reports/960020.ps.Z, 19960711 A Simple Algorithmically Reasoned Characterization of Wait-free Computations (Extended Abstract) Elizabeth Borowsky (borowsky@hpl.hp.com) Hewlett-Packard Laboratories Palo-Alto, CA 94303 U.S.A. Eli Gafni (eli@cs.ucla.edu) Computer Science Department University of California, Los Angeles Los Angeles, CA
	ftp://ftp.cs.ucla.edu/tech-report/96-reports/960026.ps.Z, 19960711 1 of 12 Divide-and-Conquer Techniques for Global Throughput Optimization Lisa Guerra , Miodrag Potkonjak , Jan Rabaey EECS Dept., University of California, Berkeley, CA CS Dept., University of California, Los Angeles, CA
	ftp://ftp.cs.ucla.edu/tech-report/96-reports/960024.ps.Z, 19960711 1 of 17 TSP-based algorithms for DSP scheduling Inki Hong and Miodrag Potkonjak Computer Science Dept., University of California, Los Angeles, CA
	ftp://ftp.cs.ucla.edu/tech-report/96-reports/960027.ps.Z, 19960711 Rate Based Congestion Control for Multicast ABR Traffic Dirceu CAVENDISH1, Saverio MASCOLO2, Mario GERLA1 1. Department of Computer Science, University of California,Los Angeles CA 90024, USA. Phone: (310) 825-4367. Fax: (310) 825-7578. E-mail: gerla@cs.ucla.edu 2. Dipartimento di Elettrotecnica ed
	ftp://ftp.cs.ucla.edu/tech-report/96-reports/960018.ps.Z, 19960715 Modeling, Simulation and VR Visualization of Brain Aneurysm Blood Flow UCLA Computer Science Department Technical Report 960018 Michael Ray Harreld July 1996 Contents 1 Introduction 7 1.1 Intracranial Aneurysms : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 7 1.1.1 Causes
	ftp://ftp.cs.ucla.edu/tech-report/96-reports/960029.ps.Z, 19960716 Artificial Intelligence Search Algorithms Richard E. Korf Computer Science Department University of California, Los Angeles Los Angeles, Ca. 90095 July 5, 1996 1 Introduction Search is a universal problem-solving mechanism in artificial intelligence (AI). In AI problems, the sequence of steps required
	ftp://ftp.cs.ucla.edu/tech-report/96-reports/960012.ps.Z, 19960723 An Improved Algorithm for Performance Optimal Technology Mapping with Retiming in LUT-Based FPGA Design Jason Cong and Chang Wu Department of Computer Science University of California, Los Angeles, CA 90024
	ftp://ftp.cs.ucla.edu/tech-report/96-reports/960030.ps.Z, 19960723 Performance of TCP over ATM for Various ABR Control Policies (Extended Version) Carlos M. D. Pazosz Vincenzo A. Signorey Dirceu Cavendish Jrz Mario Gerlaz z UCLA { Computer Science Department y Politecnico di Bari { DEE 405 Hilgard Ave., Los Angeles, CA 90024 Via Orabona 4, 70125, Bari Italy
	ftp://ftp.cs.ucla.edu/tech-report/96-reports/960031.ps.Z, 19960726 Peer Replication with Selective Control David Ratner Gerald J. Popeky Peter Reiher Department of Computer Science University of California, Los Angeles
	ftp://ftp.cs.ucla.edu/tech-report/96-reports/960001.ps.Z, 19960920 SP-EPRCA: an ATM Rate Based Congestion Control Scheme based on a Smith Predictor D. Cavendish, S. Mascolo, M. Gerla dirceu@cs.ucla.edu, mascolo@poliba.it, gerla@cs.ucla.edu
	ftp://ftp.cs.ucla.edu/tech-report/96-reports/960036.ps.Z, 19961003 Speedup of Distributed Programs on a Network of Shared Processors Sung Hyun Cho Department of Computer Science University of California, Los Angeles CA 90024 Email: cho@cs.ucla.edu, Phone: (310) 208-7459, Fax: (310) 825-2273
	ftp://ftp.cs.ucla.edu/tech-report/96-reports/960034.ps.Z, 19961003 University of California Los Angeles Competitive Execution in a Distributed Environment A dissertation submitted in partial satisfaction of the requirements for the degree Doctor of Philosophy in Computer Science by Sung Hyun Cho 1996 c Copyright by Sung Hyun Cho 1996 The dissertation of Sung Hyun Cho
	ftp://ftp.cs.ucla.edu/tech-report/96-reports/960035.ps.Z, 19961003 Competitive Execution of Sequential Programs on a Network of Shared Processors (To appear in ICA3PP , Singapole, June 11-13, 1996) Sung Hyun Cho Department of Computer Science University of California, Los Angeles, CA 90024-1596, USA E-mail: cho@cs.ucla.edu
	ftp://ftp.cs.ucla.edu/tech-report/96-reports/960038.ps.Z, 19961018 The construction of Huffman codes is a submodular (`convex') optimization problem over a lattice of binary trees D. Stott Parker stott@cs.ucla.edu Computer Science Department University of California Los Angeles, CA 90095-1596 Prasad Ram prasad@cp10.es.xerox.com Xerox Corporation El Segundo, CA 90245
	ftp://ftp.cs.ucla.edu/tech-report/97-reports/970001.directory/9.abs.ps, 19970108
	ftp://ftp.cs.ucla.edu/tech-report/97-reports/970001.directory/ch1.ps, 19970108 Chapter One Introduction Distributed Shared Memory (DSM) Multicomputers have the potential to provide high-performance by exploiting parallelism, while allowing the programmer to express the parallelism using the familiar shared memory programming model. The multicomputer type of system is
	ftp://ftp.cs.ucla.edu/tech-report/97-reports/970001.directory/TOT.ps, 19970108 List of Tables 3.1 Comparison of the storage overhead in the one-level and two-level schemes .................................................................................. 45 4.1 Deadlock due to contention for physical resources ............................. 69 4.2 access_permits of a block
	ftp://ftp.cs.ucla.edu/tech-report/97-reports/970001.directory/ch2.ps, 19970108 Chapter Two Distributed Shared Memory Issues Distributed shared memory provides a virtual machine where processes executing on all nodes share a common address space. The shared address space is physically distributed among the nodes in the system. In most implementations of DSM, the distributed address
	ftp://ftp.cs.ucla.edu/tech-report/97-reports/970001.directory/2.sig.ps, 19970108 The dissertation of G. Janakiraman is approved. hhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhh Ivo Welch hhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhh David A. Rennels hhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhh Milos D. Ercegovac hhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhh Yuval Tamir, Committee Chair University of
	ftp://ftp.cs.ucla.edu/tech-report/97-reports/970001.directory/1.cpt.ps, 19970108 Copyright by G. Janakiraman 1997
	ftp://ftp.cs.ucla.edu/tech-report/97-reports/970001.directory/0.ttl.ps, 19970108 UNIVERSITY OF CALIFORNIA Los Angeles Hierarchically Managed Reliable Distributed Shared Memory Multicomputers A dissertation submitted in partial satisfaction of the requirements for the degree Doctor of Philosophy in Computer Science by G. Janakiraman 1997
	ftp://ftp.cs.ucla.edu/tech-report/97-reports/970001.directory/7.ack.ps, 19970108 ACKNOWLEDGMENTS I have been fortunate to have had the valuable guidance of a number of people in pursuing my research aspirations. The camaraderie of many more has also made the whole experience enjoyable. I wish to express my gratitude for all their support. A large part of my research accomplishments
	ftp://ftp.cs.ucla.edu/tech-report/97-reports/970001.directory/3.ded.ps, 19970108 To my parents, who have given me everything, and my brothers, sisters, nieces and nephews, who have been waiting with eagerness. iii
	ftp://ftp.cs.ucla.edu/tech-report/97-reports/970001.directory/TOC.ps, 19970108 Table of Contents Chapter One - Introduction ......................................................................... 1 1.1. Hierarchically Managed DSM ............................................................ 4 1.2. Reliable DSM
	ftp://ftp.cs.ucla.edu/tech-report/97-reports/970001.directory/TOF.ps, 19970108 List of Figures 1.1 Multicomputer ..................................................................................... 2 2.1 System with shared bus for snoop-based coherence protocols ............ 13 2.2 Centralized directory for directory-based coherence protocol ............ 14 2.3 Distributed
	ftp://ftp.cs.ucla.edu/tech-report/97-reports/970001.directory/8.vit.ps, 19970108 VITA October 24, 1966 Born in Madras, India 1988 B.E. (Hons.) Electrical and Electronics Engineering Birla Institute of Technology and Science Pilani, India 1988 M.Sc. (Tech.) Computer Science Birla Institute of Technology and Science Pilani, India 1984-1988 BITS Merit Scholarship Birla Institute of
	ftp://ftp.cs.ucla.edu/tech-report/96-reports/960032.ps.Z, 19970111 Deadlock Resolution in Networks Employing Connection-Based Adaptive Routing Yoshio F. Turner and Yuval Tamir Computer Science Department UCLA Los Angeles, CA 90095
	ftp://ftp.cs.ucla.edu/tech-report/96-reports/960042.ps.Z, 19970115 Finding Optimal Solutions to Rubik's Cube Using Memory-Based Heuristics Richard E. Korf Computer Science Department University of California, Los Angeles Los Angeles, Ca. 90095 korf@cs.ucla.edu
	ftp://ftp.cs.ucla.edu/tech-report/96-reports/960039.ps.Z, 19970115 The Design of the FALCON Framework for Application Level Communication Optimization Eddie C. Shek, Richard R. Muntz, Larry Fillion Data Mining Laboratory Computer Science Department University of California Los Angeles, CA 90024 fshek, muntz, larryg@cs.ucla.edu November 14, 1996
	ftp://ftp.cs.ucla.edu/tech-report/96-reports/960044.ps.Z, 19970115 Implementation and Performance Evaluation of Conservative Algorithms in Parallel Simulation Languages Rajive L. Bagrodia Vikas Jha
	ftp://ftp.cs.ucla.edu/tech-report/96-reports/960040.ps.Z, 19970115 Delay Models for MCM Interconnects Under Monotone and Non-Monotone Response Andrew B. Kahng, Kei Masuko Sudhakar Muddu UCLA Computer Science Department MIPS Technologies, Silicon Graphics, Inc. Los Angeles, CA 90095-1596 Mountain View, CA 94039 abk@cs.ucla.edu, masuko@cs.ucla.edu muddu@mti.sgi.com
	ftp://ftp.cs.ucla.edu/tech-report/96-reports/960043.ps.Z, 19970115 Simultaneous Events and Lookahead in Simulation Protocols Vikas Jha Rajive Bagrodia University of California at Los Angeles
	ftp://ftp.cs.ucla.edu/tech-report/96-reports/960051.ps.Z, 19970116 System-Level Synthesis of Low-Power Hard Real-Time Systems
	ftp://ftp.cs.ucla.edu/tech-report/96-reports/960045.ps.Z, 19970116 The Ward Model: A Replication Architecture for Mobile Environments David Ratner Gerald J. Popeky Peter Reiher Department of Computer Science University of California, Los Angeles
	ftp://ftp.cs.ucla.edu/tech-report/96-reports/960049.ps.Z, 19970116 Efficient Block Scheduling for Programmable Embedded Processors
	ftp://ftp.cs.ucla.edu/tech-report/96-reports/960048.ps.Z, 19970116 Design Methodology and Tools for Throughput Optimization of Web Servers
	ftp://ftp.cs.ucla.edu/tech-report/96-reports/960050.ps.Z, 19970116 Design Methodology for Development of Behavioral Synthesis Generic and Synthetic Benchmarks
	ftp://ftp.cs.ucla.edu/tech-report/96-reports/960047.ps.Z, 19970116 Heterogeneous BISR-approach using System Level Synthesis Flexibility
	ftp://ftp.cs.ucla.edu/tech-report/96-reports/960046.ps.Z, 19970116 Power Optimization using Minimization of the Number of Operations
	ftp://ftp.cs.ucla.edu/tech-report/96-reports/960053.ps.Z, 19970123 University of California Los Angeles Incremental Search Methods for Real-Time Decision Making A dissertation submitted in partial satisfaction of the requirements for the degree Doctor of Philosophy in Computer Science by Joseph Carl Pemberton 1995 c Copyright by Joseph Carl Pemberton 1995 The
	ftp://ftp.cs.ucla.edu/tech-report/96-reports/960052.ps.Z, 19970129 Linear randomizing transformations: an a priori alternative to dynamic elimination strategies such as partial pivoting Brad Pierce pierce@cs.ucla.edu D. Stott Parker stott@cs.ucla.edu Computer Science Department, UCLA School of Engineering and Applied Science Los Angeles, CA 90095-1596, USA December
	ftp://ftp.cs.ucla.edu/tech-report/97-reports/970014.ps.Z, 19970404 Monte Carlo Arithmetic: a framework for the statistical analysis of roundoff error D. Stott Parker stott@cs.ucla.edu Computer Science Department University of California Los Angeles, CA 90095-1596 Paul R. Eggert eggert@twinsun.com Twin Sun, Inc. 360 N. Sepulveda Blvd., Suite 2055 El Segundo, CA
	ftp://ftp.cs.ucla.edu/tech-report/97-reports/970012.ps.Z, 19970404 Quadratic Placement Revisited M1.3 : Methodology (Techniques for Deep-Submicron Placement)
	ftp://ftp.cs.ucla.edu/tech-report/97-reports/970002.ps.Z, 19970408 Monte Carlo Arithmetic: exploiting randomness in floating-point arithmetic D. Stott Parker stott@cs.ucla.edu Computer Science Department University of California Los Angeles, CA 90095-1596 March 30, 1997
	ftp://ftp.cs.ucla.edu/tech-report/97-reports/970004.ps.Z, 19970408 PERFORMANCE DRIVEN GLOBAL ROUTING FOR STANDARD CELL DESIGN Jason Cong Patrick H. Madden April 7, 1997
	ftp://ftp.cs.ucla.edu/tech-report/97-reports/970010.ps.Z, 19970408 UCLA Computer Science Dept. Technical Report TR-970010 Copyright 1997 by John Peck and Jason Cong. 1 On Acceleration of Logic Synthesis Algorithms using FPGA-based Reconfigurable Coprocessors Technical Report: TR-970010 Jason Cong and John Peck Department of Computer Science University of California,
	ftp://ftp.cs.ucla.edu/tech-report/97-reports/970011.ps.Z, 19970410 FPGA Synthesis with Retiming and Pipelining for Clock Period Minimization of Sequential Circuits Jason Cong and Chang Wu Department of Computer Science University of California, Los Angeles, CA 90095 March 25, 1997
	ftp://ftp.cs.ucla.edu/tech-report/97-reports/970015.ps.Z, 19970527 Seer: Predictive File Hoarding for Disconnected Mobile Operation Geoffrey H. Kuenning University of California, Los Angeles May, 1997 A dissertation submitted in partial satisfaction of the requirements for the degree Doctor of Philosophy in Computer Science UCLA Computer Science Department Technical
	ftp://ftp.cs.ucla.edu/pub/ficus/geoff/ucla_csd_970015.ps.gz, 19970527 Seer: Predictive File Hoarding for Disconnected Mobile Operation Geoffrey H. Kuenning University of California, Los Angeles May, 1997 A dissertation submitted in partial satisfaction of the requirements for the degree Doctor of Philosophy in Computer Science UCLA Computer Science Department Technical
	ftp://ftp.cs.ucla.edu/pub/ficus/geoff/kuenning_dissertation.ps.gz, 19970527 University of California Los Angeles Seer: Predictive File Hoarding for Disconnected Mobile Operation A dissertation submitted in partial satisfaction of the requirements for the degree Doctor of Philosophy in Computer Science by Geoffrey Houston Kuenning 1997 c Copyright by Geoffrey Houston Kuenning
	ftp://ftp.cs.ucla.edu/tech-report/97-reports/970017.ps.Z, 19970604 University of California Los Angeles Virtual Reality Simulation of the Ophthalmoscopic Examination A thesis submitted in partial satisfaction of the requirements for the degree Master of Science in Computer Science by Daren Andrew Lee 1997 c Copyright by Daren Andrew Lee 1997 The thesis of Daren Andrew
	ftp://ftp.cs.ucla.edu/pub/ficus/sans2.ps.gz, 19970609 Truffles Secure File Sharing With Minimal System Administrator Intervention Peter Reiher Thomas Page, Jr. Gerald Popek UCLA Los Angeles, CA Jeff Cook Trusted Information Systems Los Angeles, CA Stephen Crocker Trusted Information Systems Glenwood, MD
	ftp://ftp.cs.ucla.edu/tech-report/97-reports/970016.ps.Z, 19970613 A Framework for the Intelligent Visualization of Large Time-Dependent Flow Datasets in Medical VR Systems Damon S.M. Liu and Walter J. Karplus Computer Science Department University of California, Los Angeles fdamon, karplusg@cs.ucla.edu Daniel J. Valentino Dept. of Radiological Sciences University of
	ftp://ftp.cs.ucla.edu/tech-report/97-reports/970020.ps.Z, 19970703 A Complete Anytime Algorithm for Number Partitioning Richard E. Korf Computer Science Department University of California, Los Angeles Los Angeles, Ca. 90095 korf@cs.ucla.edu June 27, 1997
	ftp://ftp.cs.ucla.edu/tech-report/97-reports/970018.ps.Z, 19970703 A Simulation Framework for Evaluating Replicated Filing Environments An-I A. Wang, Peter L. Reiher, and Rajive Bagrodia Department of Computer Science University of California, Los Angeles
	ftp://ftp.cs.ucla.edu/tech-report/97-reports/970022.ps.Z, 19970703 Dynamic Version Vector Maintenance David Ratner Peter Reiher Gerald J. Popeky Department of Computer Science University of California, Los Angeles
	ftp://ftp.cs.ucla.edu/tech-report/97-reports/970021.ps.Z, 19970703 Replication Requirements in Mobile Environments David Ratner Peter Reiher Gerald J. Popeky Department of Computer Science University of California, Los Angeles
	ftp://ftp.cs.ucla.edu/tech-report/97-reports/970024.ps.Z, 19970707 A General Purpose Extended Attribute Service As A File System Layer (with an example client that implements POSIX.6 Access Control Lists) Comprehensive Project Documentation for the Master of Science Degree Jeff R. Weidner Advisor: Gerald J. Popek Computer Science Department School of Engineering and
	ftp://ftp.cs.ucla.edu/tech-report/97-reports/970026.ps.Z, 19970708 A Quantitative Approach to Development and Validation of Synthetic Benchmarks for Behavioral Synthesis
	ftp://ftp.cs.ucla.edu/tech-report/97-reports/970027.ps.Z, 19970708 A Quantitative Approach to Functional Debugging
	ftp://ftp.cs.ucla.edu/tech-report/97-reports/970025.ps.Z, 19970708 Techniques for Functional Test Pattern Execution
	ftp://ftp.cs.ucla.edu/tech-report/97-reports/970028.ps.Z, 19970708 Application-Driven Synthesis of Core-Based Systems
	ftp://ftp.cs.ucla.edu/tech-report/97-reports/970030.ps.Z, 19970716 Automated Hoarding for Mobile Computers Geoffrey H. Kuenning and Gerald J. Popeky
	ftp://ftp.cs.ucla.edu/pub/ficus/geoff/perstech97.ps.gz, 19970805 Experience with an Automated Hoarding System Geoffrey H. Kuenning, Peter Reiher, and Gerald J. Popeky
	ftp://ftp.cs.ucla.edu/pub/ficus/geoff/sosp97.ps.gz, 19970805 Automated Hoarding for Mobile Computers Geoffrey H. Kuenning and Gerald J. Popeky
	ftp://ftp.cs.ucla.edu/tech-report/97-reports/970032.ps.Z, 19970818 Design of the RIO (Randomized I/O) Storage Server Jose Renato Santos Richard Muntz
	ftp://ftp.cs.ucla.edu/tech-report/97-reports/970013.ps.Z, 19970820 UCLA Computer Science Technical Report 970013 Analysis and Justification of a Simple, Practical 2 1/2-D Capacitance Extraction Methodology Jason Congy, Lei Hey, Andrew B. Kahng, David Noice, Nagesh Shirali and Steve H.-C. Yen Cadence Design Systems, Inc., San Jose, CA 95134 yUCLA, Computer Science
	ftp://ftp.cs.ucla.edu/tech-report/97-reports/970037.ps.Z, 19971023 Asynchronous Parallel Simulation of Parallel Programs Rajive Bagrodia (rajive@cs.ucla.edu) Computer Science Department University of California Los Angeles, CA 90024 Sundeep Prakash (prakash@cs.ucla.edu) Computer Science Department University of California Los Angeles, CA 90024 June 27, 1997
	ftp://ftp.cs.ucla.edu/tech-report/97-reports/970041.ps.Z, 19971114 Cooperative Chaos Geoffrey H. Kuenning David H. Ratner Peter Reiher Gerald J. Popek Richard G. Guyy Technical Report UCLA-CSD-970041 November 14, 1997
	ftp://ftp.cs.ucla.edu/pub/ficus/geoff/ucla_csd_970041.ps.gz, 19971114 Cooperative Chaos Geoffrey H. Kuenning David H. Ratner Peter Reiher Gerald J. Popek Richard G. Guyy Technical Report UCLA-CSD-970041 November 14, 1997
	ftp://ftp.cs.ucla.edu/tech-report/97-reports/970040.ps.Z, 19971118 Yet Another Spatial Indexing Structure Jiong Yang, Wei Wang, and Richard Muntz Department of Computer Science University of California, Los Angeles fjyang,weiwang,muntzg@cs.ucla.edu November 17, 1997
	ftp://ftp.cs.ucla.edu/tech-report/97-reports/970039.ps.Z, 19971118 PK-tree: A Dynamic Spatial Index Structure for Large Data Setsy Wei Wang, Jiong Yang, and Richard Muntz Department of Computer Science University of California, Los Angeles fweiwang,jyang,muntzg@cs.ucla.edu November 17, 1997
	ftp://ftp.cs.ucla.edu/tech-report/97-reports/970042.ps.Z, 19971118 A Multidimensional Study on Parallel Switch-Level Circuit Simulation Yu-an Chen and Rajive Bagrodia Computer Science Department University of California at Los Angeles Los Angeles, CA90024
	ftp://ftp.cs.ucla.edu/tech-report/97-reports/970033.ps.Z, 19971119 Interconnect Layout Optimization Under Higher-Order RLC Model Jason Cong and Cheng-Kok Koh UCLA Computer Science Dept., Los Angeles, CA 90095-1596
	ftp://ftp.cs.ucla.edu/tech-report/97-reports/970044.ps.Z, 19980113 Roam: A Scalable Replication System for Mobile and Distributed Computing David Howard Ratner University of California, Los Angeles January, 1998 A dissertation submitted in partial satisfaction of the requirements for the degree Doctor of Philosophy in Computer Science UCLA Computer Science Department
	ftp://ftp.cs.ucla.edu/tech-report/97-reports/970031.ps.Z, 19980114 Global Interconnect Sizing and Spacing with Consideration of Coupling Capacitance Jason Cong, Lei He, Cheng-Kok Koh, and Zhigang Pan fcong, helei, kohck, pang@cs.ucla.edu Department of Computer Science University of California, Los Angeles, CA 90095 January 14, 1998
	ftp://ftp.cs.ucla.edu/tech-report/97-reports/970043.ps.Z, 19980121 On the Construction of Low Cost Multicast Trees with Bandwidth Reservation Dirceu Cavendish , Aiguo Fei, Mario Gerla Raphael Rom Department of Computer Science Faculty of Electrical Engineering University of California,Los Angeles CA 90024 Israel Institute of Technology Haifa 32000 Israel
	ftp://ftp.cs.ucla.edu/tech-report/97-reports/970038.ps.Z, 19980121 DynamO: Dynamic Objects with Network Attached Persistent Stores Jiong Yang, Wei Wang, and Richard Muntz fjyang, weiwang, muntzg@cs.ucla.edu Department of Computer Science University of California, Los Angeles January 15, 1998
	ftp://ftp.cs.ucla.edu/tech-report/97-reports/970034.ps.Z, 19980121 UCLA Computer Science Technical Report 970034 An Efficient Technique for Device and Interconnect Optimization in Deep Submicron Designs Jason Cong and Lei He Department of Computer Science University of California, Los Angeles, CA 90095
	ftp://ftp.cs.ucla.edu/tech-report/97-reports/970023.ps.Z, 19980121 Yet another analytic study of input-buffered ATM switches y Christos Kolias and Leonard Kleinrock January 20, 1998
	ftp://ftp.cs.ucla.edu/tech-report/98-reports/980008.ps.Z, 19980211 TCP CONGESTION AVOIDANCE USING EXPLICIT BUFFER NOTIFICATION by SAVERIO MASCOLO AND MARIO GERLA CSD-TR 980008 TCP Congestion Avoidance Using Explicit Buffer Notification by Saverio Mascolo and Mario Gerla 1 TCP Congestion Avoidance Using Explicit Buffer Notification Saverio Mascolo and Mario Gerla