 | ftp://ftp.eecg.toronto.edu//pub/tech_reports/TR-92-09-01.ps.Z, 19920929
Cache Consistency in Hierarchical-Ring-Based Multiprocessorsy Keith Farkas Zvonko Vranesic Michael Stumm Department of Electrical Engineering University of Toronto Toronto, Ontario, Canada M5S 1A4 email: farkas@eecg.toronto.edu EECG TR-92-09-01 |
| ftp://ftp.eecg.toronto.edu/pub/tech_reports/TR-92-09-02.ps.Z, 19921001
TEMPT: Technology Mapping for the Exploration of FPGA Architectures with Hard-Wired Connections Kevin Chung & Jonathan Rose Department of Electrical Engineering University of Toronto CANADA M5S 1A4 |
| ftp://ftp.eecg.toronto.edu/pub/tech_reports/TR-92-09-03.ps.Z, 19921005
EMI-Induced Delays in Digital Circuits: Application John F. Chappel and Safwat G. Zaky Department of Electrical Engineering, University of Toronto October 1, 1992 |
| ftp://ftp.eecg.toronto.edu/pub/tech_reports/TR-92-10-01.ps.Z, 19921009
Region-Oriented Main Memory Management in Shared-Memory NUMA Multiprocessors by Benjamin Gamsa TR-92-10-01 Department of Computer Science University of Toronto Toronto, Ontario, Canada, M5S 1A4 email: ben@cs.toronto.edu c Copyright by Benjamin Gamsa 1992 |
| ftp://ftp.eecg.toronto.edu/pub/tech_reports/TR-91-04-01.ps.Z, 19921023
A Decentralized Hierarchical Cache-Consistency Scheme For Shared-Memory Multiprocessors by Keith I. Farkas A Thesis submitted in conformity with the requirements for the Degree of Master of Applied Science in the Department of Electrical Engineering, University of Toronto TR-EECG-91-04-01 c Copyright by |
| ftp://ftp.eecg.toronto.edu/pub/tech_reports/TR-93-03-01.ps.Z, 19931015
Scalable Cache Consistency for Hierarchically-Structured Multiprocessors Keith Farkas Zvonko Vranesic Michael Stumm Department of Electrical and Computer Engineering University of Toronto Toronto, Ontario, Canada M5S 1A4 email: farkas@eecg.toronto.edu March 30, 1993 |
| ftp://ftp.eecg.toronto.edu/pub/tech_reports/TR-93-06-01.ps.Z, 19931015
Technology Mapping for Lookup-Table Based Field-Programmable Gate Arrays by Robert J. Francis A thesis submitted in conformity with the requirements for the degree of Doctor of Philosophy Graduate Department of Electrical Engineering Computer Group University of Toronto Toronto, Ontario Canada c Robert |
| ftp://ftp.eecg.toronto.edu/pub/tech_reports/SteveBrown/stochastic.ps.Z, 19940614
A Stochastic Model to Predict the Routability of Field-Programmable Gate Arrays Stephen D. Brown, Jonathan Rose and Zvonko G. Vranesic Department of Electrical Engineering University of Toronto, Canada |
| ftp://ftp.eecg.toronto.edu/pub/tech_reports/SteveBrown/cicc94.fm.ps.Z, 19940614
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| ftp://ftp.eecg.toronto.edu/pub/tech_reports/SteveBrown/vlsidsgn.ps.Z, 19940803
Page 1 of 24 Segmented Routing for Speed-Performance and Routability in Field-Programmable Gate Arrays Stephen Brown, Muhammad Khellah, and Guy Lemieux Department of Electrical and Computer Engineering University of Toronto, Canada E-mail: brown@eecg.toronto.edu |
| ftp://ftp.eecg.toronto.edu//pub/tech_reports/CGLee/PhDthesis.ps.Z, 19941028
Code Optimizers and Register Organizations for Vector Architectures Corinna Grace Lee May 7, 1992 Code Optimizers and Register Organizations for Vector Architectures Copyright c 1992 by Corinna Grace Lee iii Code Optimizers and Register Organizations for Vector Architectures Corinna Grace Lee Computer |
| ftp://ftp.eecg.toronto.edu/pub/tech_reports/SteveWilton/twolevel.ps.Z, 19941111
Tradeoffs in Two-Level On-Chip Caching Norman P. Jouppi Steven J. E. Wilton Digital Equipment Corporation University of Toronto Western Research Lab Dept. Electrical and Computer Engineering 250 University Avenue 10 King's College Rd Palo Alto, CA 94301 Toronto, Ontario, Canada jouppi@pa.dec.com M5S 1A4 |
| ftp://ftp.eecg.toronto.edu/pub/tech_reports/dunc/peta95.slides2up.ps, 19950203
1 A PetaOp/s is Currently Feasible by Computing in RAM Duncan G. Elliott W. Martin Snelgrove Christian Cojocaru Michael Stumm Department of Electrical & Computer Engineering, University of Toronto Department of Electronics, Carleton University Building Smart Memories with SIMD processors at the |
| ftp://ftp.eecg.toronto.edu//pub/tech_reports/SteveBrown/ccvlsi.ps.Z, 19950412
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| ftp://ftp.eecg.toronto.edu/pub/tech_reports/SteveBrown/fpd.ps.Z, 19950908
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| ftp://ftp.eecg.toronto.edu//pub/sun-dist/hub-ether.ps, 19960129
godzillamedusarobsonugsparc10cyanvrg-etherant-etherecf-ethercsri1-ethercsri2-etherhub-ethercad1-ethercad-ether GATEWAYS ATTACHED TO HUB-ETHER |
| ftp://ftp.eecg.toronto.edu//pub/tech_reports/RalphWittig/slides.thumbnail.ps, 19960315
RDW 1995 . . . 1/21 University of Toronto OneChip: An FPGA Processor With Reconfigurable Logic Ralph D. Wittig M.A.Sc. Thesis Oral Presentation Department of Electrical & Computer Engineering September 1995 RDW 1995 . . . 2/21 University of Toronto Motivation Computing: 1. FPGAs 4 save logic development |
| ftp://ftp.eecg.toronto.edu//pub/tech_reports/RalphWittig/slides.ps, 19960315
RDW 1995 . . . 21/21 University of Toronto Future Work custom silicon OneChip implementation overcome TM-1 limitations OneChip specific hardware optimizations prototype extension additional fixed instructions complete register file cache / multi-level memory system superscalar, time-shared OneChip |
| ftp://ftp.eecg.toronto.edu/pub/tech_reports/RalphWittig/thesis.ps, 19960315
OneChip: An FPGA Processor With Reconfigurable Logic by Ralph D. Wittig A thesis submitted in conformity with the requirements for the degree of Master of Applied Science in the Department of Electrical and Computer Engineering, University of Toronto Copyright by Ralph D. Wittig 1995 ii iii OneChip: An |
| ftp://ftp.eecg.toronto.edu/pub/tech_reports/dunc/peta95.paper.ps, 19960428
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| ftp://ftp.eecg.toronto.edu//pub/tech_reports/dunc/cicc92.ps, 19960512
page 1/4 Computational Ram: A Memory-SIMD Hybrid and its Application to DSP Duncan G. Elliott, W. Martin Snelgrove and Michael Stumm Department of Electrical Engineering, University of Toronto Toronto, Canada M5S 1A4 (416)978-3381 Computational RAM (CfflRAM) is conventional RAM with SIMD processors |
