Clock Synchronization UNIT

(CSU)?

Datasheet

Institut f?ur Technische Informatik

Technical University Vienna

Austria

Nov. 1989

Features

ffl Clock synchronization by means of automatic variation of the duration between two clock ticks

ffl Programmable correction of clock state and clock rate

ffl Two state registers with different resolutions (1?s and 100?s) available

ffl Programmable output interrupt mode and period

ffl Sample and hold register for the accurate determination of an interrupt signal (e.g. arrival time of an incoming message)

ffl DMA compatible interface, such that the CSU registers can be accessed with a memory fetch operation (e.g. in order to timestamp an outgoing message)

ffl Programmable timeout support

ffl Processor independent peripheral device

ffl 16 bit databus

ffl Single 5V power supply

ffl 28 pin dual-in-line package

?The CSU is produced by Austria Mikro Systeme International GmbH with the chip number "S65C60".

Applications

ffl Realization of a logical clock whose state can be corrected and rate can be readjusted

ffl Efficient implementation of a fault-tolerant global time base by synchronization of the local clocks of each node in a distributed system

ffl Measurement of accurate arrival times of events

General Description

The Clock Synchronization Unit (CSU) is a peripheral device for 16 bit microprocessor. It is produced in a 28 pin dual-in-line package (see figure 1).

The objectives of the CSU are:

ffl to provide a global time reference in a distributed real-time computer system

ffl to improve the synchronization accuracy

ffl to reduce the CPU load for clock synchronization

The CSU (see figure 2) provides a high resolution register with a granularity of 1?s and a low resolution register with a granularity of 100?s.