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The Boyer-Moore Prover and Nuprl: An Experimental Comparison Technical Report #58 29 Per Martin-L of. Constructive mathematics and computer programming." In Sixth International Congress for Logic, Methodology, and Philosophy of Science, pages 15375, North Holland, Amsterdam, 1982. J.
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A Formal Introduction to a Simple HDL Bishop C. Brock and Warren A. Hunt, Jr. Technical Report 60 July 31, 1990 Computational Logic, Inc. 1717 West Sixth Street, Suite 290 Austin, Texas 78703-4776 TEL: +1 512 322 9951 FAX: +1 512 322 0656 EMAIL: brock@cli.com, hunt@cli.com This paper appears in the
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Functional Instantiation in First Order Logic Technical Report #44 35 research reported here. The views and conclusions contained herein are those of the authors and should not be interpreted as representing the official policies, either expressed or implied, of the Defense Advanced Research Projects
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Mathematical Methods for Digital Systems Development Technical Report #67 23 Matt Kaufmann, A User's Manual for an Interactive Enhancement to the Boyer-Moore Theorem Prover," Technical Report 19, Computational Logic, Inc., 1988. J Strother Moore, A Mechanically Verified Language
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Computational Logic Inc. 1717 W. 6th St. Suite 290 Austin, Texas 78703 (512) 322-9951 NASA Contractor Report 189588 Mechanically Verified Hardware Implementing an 8-Bit Parallel IO Byzantine Agreement Processor J Strother Moore Computational Logic, Inc. Austin, Texas Contract NAS1-18878 1992
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An Introduction to a Formally Defined Hardware Description Language Technical Report #76 37 David J. Kuck. The Structure of Computers and Computations, John Wiley & Sons: New York, 1978. Beth H. Levy. An Overview of Hardware Verification using the State Delta Verification System (SDVS), in
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A Formal HDL and its use in the FM9001 Verification Technical Report #79 17 Steven D. Johnson. Manipulating logical organization with system factorizations. In Hardware Specification, Verification and Synthesis: Mathematical Aspects., volume 408 of Lecture Notes in Computer Science, pages 25980.
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A Mechanically Verified Application for a Mechanically Verified Environment Matthew Wilding Computational Logic Inc., 1717 West Sixth Street Suite 290, Austin Texas, USA and The University of Texas at Austin
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AUTOMATED PROOFS OF OBJECT CODE FOR A WIDELY USED MICROPROCESSOR Publication No. Yuan Yu, Ph.D. The University of Texas at Austin, 1992 Supervisor: Robert S. Boyer Computing devices can be specified and studied mathematically. Formal specification of computing devices has many advantages { it provides a
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NASA Contractor Report 191509 A Formal Language for the Specification and Verification of Synchronous and Asynchronous Circuits David M. Russinoff COMPUTATIONAL LOGIC, INC. Austin, Texas Contract NAS1-18878 September 1993 NASA Contractor Report 191509 A Formal Language for the Specification and
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A Formalization of a Subset of VHDL David M. Russinoff Technical Report 98 May 10, 1994 Computational Logic, Inc. 1717 West Sixth Street, Suite 290 Austin, Texas 78703-4776 TEL: +1 512 322 9951 FAX: +1 512 322 0656 EMAIL: russ@cli.com This work was sponsored in part at Computational Logic, Inc. by
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Interaction with the Boyer-Moore Theorem Prover: A Tutorial Study Using the Arithmetic-Geometric Mean Theorem Matt Kaufmann (CLI) and Paolo Pecchiari (IRST, DIST) Technical Report 100 August, 1994 Computational Logic, Inc. 1717 West Sixth Street, Suite 290 Austin, Texas 78703-4776 TEL: +1 512 322 9951
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Design Goals for ACL2 Matt Kaufmann and J Strother Moore Technical Report 101 August, 1994 Computational Logic, Inc. 1717 West Sixth Street, Suite 290 Austin, Texas 78703-4776 TEL: +1 512 322 9951 FAX: +1 512 322 0656 EMAIL: kaufmann@cli.com and moore@cli.com This work was supported in part at
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Mechanically Verifying Safety and Liveness Properties of Delay Insensitive Circuits David M. Goldschlag Technical Report 66 March, 1991 Computational Logic Inc. 1717 W. 6th St. Suite 290 Austin, Texas 78703 (512) 322-9951 This work was supported in part at Computational Logic, Inc., by the Defense
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A Mechanically-Checked Correctness Proof of a Floating-Point Search Program Matt Wilding Technical Report #56 May, 1990 Computational Logic Inc. 1717 W. 6th St. Suite 290 Austin, Texas 78703 (512) 322-9951 This work was supported in part at Computational Logic, Inc., by the Defense Advanced Research
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The Proof of Correctness of a Fault-Tolerant Circuit Design William R. Bevier William D. Young Technical Report 57 August 1990 Computational Logic Inc. 1717 W. 6th St. Suite 290 Austin, Texas 78703 (512) 322-9951 This work was sponsored in part at Computational Logic, Inc. by National Aeronautics and
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Predicting Computer Behavior Donald I. Good Technical Report 20Technical Report 20 May 1988May 1988 Computational Logic Inc. 1717 W. 6th St. Suite 290 Austin, Texas 78703 (512) 322-9951 This work was sponsored in part by the Defense Advanced Research Projects Agency under ARPA Orders 6082 and 9151. The
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Mathematical Forecasting Donald I. Good Technical Report 47 September 1989 Computational Logic Inc. 1717 W. 6th St. Suite 290 Austin, Texas 78703 (512) 322-9951 This report is to appear in a forthcoming American Institute of Aeronautics and Astronautics (AIAA) Progress Series book on Aerospace Software
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Technical Report 96 December 30, 1993 Computational Logic Inc. 1717 W. 6th St. Suite 290 Austin, Texas 78703 (512) 322-9951 This work was supported in part at Computational Logic, Inc., by the Defense Advanced Research Projects Agency, ARPA Order 7406. The views and conclusions contained in this
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Technical Report 70 September, 1991 Computational Logic Inc. 1717 W. 6th St. Suite 290 Austin, Texas 78703 (512) 322-9951 This work was sponsored in part at Computational Logic, Inc. by the Naval Research Laboratory, contract number N00014-90-C-2351 and is the final report on Task 1 of this contract.
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Technical Report 50 November, 1989 Computational Logic Inc. 1717 W. 6th St. Suite 290 Austin, Texas 78703 (512) 322-9951 This work was supported in part at Computational Logic, Inc., by the Defense Advanced Research Projects Agency, ARPA Orders 6082 and 9151. The views and conclusions contained in this
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A Mechanically Verified Proof System for Concurrent Programs David M. Goldschlag Technical Report 32 January, 1989 Computational Logic Inc. 1717 W. 6th St. Suite 290 Austin, Texas 78703 (512) 322-9951 This work was supported in part at Computational Logic, Inc., by the Defense Advanced Research Projects
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Technical Report 82 September 1992 Computational Logic Inc. 1717 W. 6th St. Suite 290 Austin, Texas 78703 (512) 322-9951 This work was supported in part at Computational Logic, Inc., by the Defense Advanced Research Projects Agency, ARPA Order 7406. The views and conclusions contained in this document
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Technical Report 71 May, 1992 Computational Logic Inc. 1717 W. 6th St. Suite 290 Austin, Texas 78703 (512) 322-9951 This work, originally presented as a Ph.D. thesis at the University of Texas at Austin, was sponsored in part at Computational Logic, Inc. by the Defense Advanced Research Projects Agency,
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The Underlying Semantics of Transition Systems J. M. Crawford D. M. Goldschlag Technical Report 17 December 1987 Computational Logic Inc. 1717 W. 6th St. Suite 290 Austin, Texas 78703 (512) 322-9951 1 Acknowledgements Crawford's work was sponsored in part at the University of Texas at Austin by Navy
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A Mechanically Verified Language Implementation J Strother Moore Technical Report 30 September, 1988 Computational Logic Inc. 1717 W. 6th St. Suite 290 Austin, Texas 78703 (512) 322-9951 This work was supported in part at Computational Logic, Inc., by the Defense Advanced Research Projects Agency, ARPA
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Microprocessor Design Verification Warren A. Hunt, Jr. Copyright 1989 Warren A. Hunt, Jr. Technical Report 48 September 1989 Computational Logic Inc. 1717 W. 6th St. Suite 290 Austin, Texas 78703 (512) 322-9951 This report will appear in a Fall 1989 issue of the Journal of Automated Reasoning. This work
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Technical Report 75 March, 1992 Computational Logic Inc. 1717 W. 6th St. Suite 290 Austin, Texas 78703 (512) 322-9951 This work was supported in part at Computational Logic, Inc., by the Defense Advanced Research Projects Agency, ARPA Order 7406. The views and conclusions contained in this document are
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NASA Contractor Report 182099 Machine Checked Proofs of the Design and Implementation of a Fault-Tolerant Circuit William R. Bevier William D. Young Computational Logic, Inc. Austin, Texas Contract NAS1-18878 November 1990
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Technical Report 85 November, 1992 Computational Logic Inc. 1717 W. 6th St. Suite 290 Austin, Texas 78703 (512) 322-9951 This work was supported in part at Computational Logic, Inc., by the Defense Advanced Research Projects Agency, ARPA Order 7406. The views and conclusions contained in this document
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The Verification of a Bit-slice ALU Warren A. Hunt, Jr. Bishop C. Brock Technical Report 49 September 1989 Computational Logic Inc. 1717 W. 6th St. Suite 290 Austin, Texas 78703 (512) 322-9951 This paper was presented at the "Workshop on Hardware Specification, Verification and Synthesis: Mathematical
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A Parallel Version of the Boyer-Moore Prover Matt Kaufmann Matt Wilding Technical Report 39 February 1989 This research was supported in part by ONR Contract N00014-88-C-0454. The views and conclusions contained in this document are those of the authors and should not be interpreted as representing the
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A User's Manual for an Interactive Enhancement to the Boyer-Moore Theorem Prover Matt Kaufmann Technical Report #19 May 1988 Computational Logic Inc. 1717 W. 6th St. Suite 290 Austin, Texas 78703 (512) 322-9951 Acknowledgements An early version of part of this system was written by J Moore, who I also
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An Approach to Systems Verification William R. Bevier, Warren A. Hunt, Jr., J Strother Moore, William D. Young Technical Report 41 April, 1989 Computational Logic Inc. 1717 W. 6th St. Suite 290 Austin, Texas 78703 (512) 322-9951 This work was supported in part at Computational Logic, Inc., by the
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The Formalization of a Simple Hardware Description Language Bishop C. Brock Warren A. Hunt, Jr. Technical Report 52 November 1989 Computational Logic Inc. 1717 W. 6th St. Suite 290 Austin, Texas 78703 (512) 322-9951 This work was sponsored in part at Computational Logic, Inc., by the Defense Advanced
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The Formal Specification and Definition of KIT William R. Bevier Technical Report 16 December, 1987 Computational Logic Inc. 1717 W. 6th St. Suite 290 Austin, Texas 78703 (512) 322-9951 This work was sponsored in part by the Department of the Navy, Naval Electronic Systems Command, contract
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Technical Report 72 January, 1992 Computational Logic Inc. 1717 W. 6th St. Suite 290 Austin, Texas 78703 (512) 322-9951 This work was supported in part at Computational Logic, Inc., by the Defense Advanced Research Projects Agency, ARPA Order 7406. The views and conclusions contained in this document
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Comparing Specification Paradigms: Gypsy and Z William D. Young Technical Report 45 June, 1989 This paper will be presented at the 12th National Computer Security Conference, Baltimore, Maryland, October 10-13, 1989. Computational Logic Inc. 1717 W. 6th St. Suite 290 Austin, Texas 78703 (512) 322-9951
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Technical Report 73 January, 1992 Computational Logic Inc. 1717 W. 6th St. Suite 290 Austin, Texas 78703 (512) 322-9951 This work was supported in part at Computational Logic, Inc., by the Defense Advanced Research Projects Agency, ARPA Order 7406. The views and conclusions contained in this document
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A Verified Code Generator for a Subset of Gypsy William D. Young Technical Report 33 October 1988 Computational Logic Inc. 1717 W. 6th St. Suite 290 Austin, Texas 78703 (512) 322-9951 This research was supported in part by the U.S. Government. The views and conclusions contained in this document are
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Addition of Free Variables to the PC-NQTHM Interactive Enhancement of the Boyer-Moore Theorem Prover Matt Kaufmann Technical Report #42 May, 1989 (revised March, 1990) Computational Logic Inc. 1717 W. 6th St. Suite 290 Austin, Texas 78703 (512) 322-9951 This research was supported in part by ONR
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DEFN-SK: An Extension of the Boyer-Moore Theorem Prover to Handle First-Order Quantifiers ***DRAFT*** Matt Kaufmann Technical Report #43 May, 1989 Computational Logic Inc. 1717 W. 6th St. Suite 290 Austin, Texas 78703 (512) 322-9951 This research was supported in part by ONR Contract N00014-88-C-0454.
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Technical Report 84 October, 1992 Computational Logic Inc. 1717 W. 6th St. Suite 290 Austin, Texas 78703 (512) 322-9951 The views and conclusions contained in this document are those of the author and should not be interpreted as representing the official policies, either expressed or implied, of
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Technical Report 81 August, 1992 Computational Logic Inc. 1717 W. 6th St. Suite 290 Austin, Texas 78703 (512) 322-9951 This research was supported in part by ONR Contract N00014-91-C-0130. The views and conclusions contained in this document are those of the author(s) and should not be interpreted as
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A Verified Operating System Kernel William R. Bevier Technical Report 11 October, 1987 Computational Logic Inc. 1717 W. 6th St. Suite 290 Austin, Texas 78703 This work was sponsored in part by the University of (512) 322-9951 Texas at Austin by the Defense Advanced Research Projects Agency, ARPA Order
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The Partial Specification of Microprocessor Instruction Set Architectures William R. Bevier Technical Report 51 November 1989 Computational Logic Inc. 1717 W. 6th St. Suite 290 Austin, Texas 78703 (512) 322-9951 This work was sponsored in part at Computational Logic, Inc., by the Defense Advanced
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Technical Report: 64 February 1992 Computational Logic Inc. 1717 W. 6th St. Suite 290 Austin, Texas 78703 (512) 322-9951 This document is derived from the on-line version of the Ada Reference Manual (ANSI/MIL-STD-1815A-1983) available at ajpo.sei.cmu.edu. This work was sponsored in part by the Defense
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Kit: A Study in Operating System Verification William R. Bevier Technical Report 28 August, 1988 Computational Logic Inc. 1717 W. 6th St. Suite 290 Austin, Texas 78703 (512) 322-9951 This research was supported in part by the U.S. Government. The views and conclusions contained in this document are
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The nanoAVA Definition Dan Craigen, Mark Saaltink, Michael K. Smith Technical Report 21 June, 1988 Computational Logic Inc. 1717 W. 6th St. Suite 290 Austin, Texas 78703 (512) 322-9951 This work was sponored in part by the Defense Advanced Research Projects Agency, ARPA Orders 6082 and 9151. The views
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Computational Logic Inc. 1717 W. 6th St. Suite 290 Austin, Texas 78703 (512) 322-9951 This research was supported in part by the U.S. Government. The views and conclusions contained in this document are those of the authors and should not be intepreted as representing the official policies, either
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IDM -- A Configuration Management Tool for Maintaining Consistency Through Incremental Development May 1, 1989 Technical Report #40 Robert L. Akers Lawrence M. Smith Computational Logic Inc. 1717 W. 6th St. Suite 290 Austin, Texas 78703 (512) 322-9951 This research was supported in part by the Defense
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Technical Report #36 March 1, 1984 Computational Logic Inc. 1717 W. 6th St. Suite 290 Austin, Texas 78703 (512) 322-9951 This report is an unrevised edition of Technical Report 41, Institute for Computing Science and Computer Applications, The University of Texas at Austin. The original paper was
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A Theorem Prover for a Computational Logic 1 Robert S. Boyer J Strother Moore Technical Report 54 April, 1990 Computational Logic Inc. 1717 W. 6th St. Suite 290 Austin, Texas 78703 (512) 322-9951 This report was the keynote address at the 10th International Conference on Automated Deduction, July, 1990
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Technical Report 91 May 1993 Computational Logic Inc. 1717 W. 6th St. Suite 290 Austin, Texas 78703 (512) 322-9951 This work was supported in part at Computational Logic, Inc., by the Defense Advanced Research Projects Agency, ARPA Order 7406. The views and conclusions contained in this document are
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Piton: A Verified Assembly Level Language by J Strother Moore Technical Report 22 September, 1988 This work was supported in part at Computational Logic, Inc., by the Defense Advanced Research Projects Agency, ARPA Orders 6082 and 9151. The views and conclusions contained in this document are those of
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A Mechanical Formalization of Several Fairness Notions David M. Goldschlag Technical Report 65 March, 1991 Computational Logic Inc. 1717 W. 6th St. Suite 290 Austin, Texas 78703 (512) 322-9951 This work was supported in part at Computational Logic, Inc., by the Defense Advanced Research Projects Agency,
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Technical Report 74 January, 1992 Computational Logic Inc. 1717 W. 6th St. Suite 290 Austin, Texas 78703 (512) 322-9951 This work was supported in part at Computational Logic, Inc., by the Defense Advanced Research Projects Agency, ARPA Order 7406. The views and conclusions contained in this document
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1 The Mechanical Verification of Distributed Systems J. M. Crawford D. M. Goldschlag Technical Report #7 July 1987 Computational Logic, Inc. 1717 West Sixth Street Suite 290 Austin, Texas 78703 Computational Logic Inc. 1717 W. 6th St. Suite 290 Austin, Texas 78703 (512) 322-9951 2 Acknowledgements At
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Generalization in the Presence of Free Variables: a Mechanically-Checked Correctness Proof for One Algorithm Matt Kaufmann Technical Report #53 April, 1990 Computational Logic Inc. 1717 W. 6th St. Suite 290 Austin, Texas 78703 (512) 322-9951 This research was supported in part by ONR Contract
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Middle Gypsy 2.05 Definition Donald I. Good Ann E. Siebert William D. Young Technical Report 59 15 May 1990 Computational Logic Inc. 1717 W. 6th St. Suite 290 Austin, Texas 78703 (512) 322-9951
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A Mechanically Verified Code Generator William D. Young Technical Report 37 January, 1989 Computational Logic Inc. 1717 W. 6th St. Suite 290 Austin, Texas 78703 (512) 322-9951 This work was supported in part at Computational Logic, Inc. by the Defense Advanced Research Projects Agency, ARPA Orders 6082
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Modeling and Verification of a Simple Real-Time Railroad Gate Controller William D. Young Technical Report 93 September, 1994 Computational Logic, Inc. 1717 West Sixth Street, Suite 290 Austin, Texas 78703-4776 TEL: +1 512 322 9951 FAX: +1 512 322 0656 EMAIL: young@cli.com This research was supported in
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Technical Report 68 1992 Computational Logic Inc. 1717 W. 6th St. Suite 290 Austin, Texas 78703 (512) 322-9951 A Formal Model of Asynchronous Communication and Its Use in Mechanically Verifying a Biphase Mark Protocol J Strother Moore
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Specification and Verification of Gate-Level VHDL Models of Synchronous and Asynchronous Circuits David M. Russinoff Technical Report 99 May 10, 1994 Computational Logic, Inc. 1717 West Sixth Street, Suite 290 Austin, Texas 78703-4776 TEL: +1 512 322 9951 FAX: +1 512 322 0656 EMAIL: russ@cli.com This
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A Mathematical Model of the Mach Kernel: Atomic Actions and Locks William R. Bevier and Lawrence M. Smith Technical Report 89 November 18, 1994 Computational Logic, Inc. 1717 West Sixth Street, Suite 290 Austin, Texas 78703-4776 TEL: +1 512 322 9951 FAX: +1 512 322 0656 EMAIL: bevier@cli.com,
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A Verified Implementation of an Applicative Language with Dynamic Storage Allocation Arthur D. Flatau Technical Report 83 January 6, 1993 Computational Logic, Inc. 1717 West Sixth Street, Suite 290 Austin, Texas 78703-4776 TEL: +1 512 322 9951 FAX: +1 512 322 0656 EMAIL: flatau@cli.com This work was
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A Mathematical Model of the Mach Kernel: Entities and Relations William R. Bevier and Lawrence M. Smith Technical Report 88 December, 1994 Computational Logic, Inc. 1717 West Sixth Street, Suite 290 Austin, Texas 78703-4776 TEL: +1 512 322 9951 FAX: +1 512 322 0656 EMAIL: bevier@cli.com, lsmith@cli.com.
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Report on the Formal Specification and Partial Verification of the VIPER Microprocessor Bishop Brock Warren A. Hunt, Jr.1 Technical Report 46 January 15, 1990 Computational Logic, Inc. 1717 West Sixth Street, Suite 290 Austin, Texas 78703-4776 TEL: +1 512 322 9951 FAX: +1 512 322 0656 EMAIL:
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The FM9001 Microprocessor Proof Bishop C. Brock, Warren A. Hunt, Jr., Matt Kaufmann Technical Report 86 December 23, 1994 Computational Logic, Inc. 1717 West Sixth Street, Suite 290 Austin, Texas 78703-4776 TEL: +1 512 322 9951 FAX: +1 512 322 0656 EMAIL: hunt@cli.com This work was supported in part at
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Testing the FM9001 Microprocessor Kenneth L. Albin, Bishop C. Brock, Warren A. Hunt, Jr., Lawrence M. Smith Technical Report 90 January 6, 1995 Computational Logic, Inc. 1717 West Sixth Street, Suite 290 Austin, Texas 78703-4776 TEL: +1 512 322 9951 FAX: +1 512 322 0656 EMAIL: hunt@cli.com This work was
open this document and view contentsftp://www.cli.com/pub/reports/113.ps, 19960522
Annotated AVA 95 Reference Manual Language and Standard Libraries Modifications by Michael K. Smith and Robert L. Akers 5 October 1995 Derived from ISO/IEC JTC1/SC22 WG9 N 193, AARM Version 6.0 CLI Technical Report 113 Computational Logic, Inc. 1717 W. 6th, Suite 290 Austin, Texas 78703 (512) 322-9951
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AVA 95 Reference Manual Language and Standard Libraries Modifications by Michael K. Smith and Robert L. Akers 5 October 1995 Derived from ISO/IEC JTC1/SC22 WG9 N 193, AARM Version 6.0 CLI Technical Report 114 Computational Logic, Inc. 1717 W. 6th, Suite 290 Austin, Texas 78703 (512) 322-9951
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Technical Report: 112 September 1995 Computational Logic Inc. 1717 W. 6th St. Suite 290 Austin, Texas 78703 (512) 322-9951 This work was sponsored in part by the Defense Advanced Research Projects Agency, ARPA Orders 6082 and 9151. The views, conclusions and modifications contained in this document are