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ftp://dit.lth.se (72)

	ftp://dit.lth.se/pub/techreports/complete-papers/Dt-060.ps.Z, 19921210 Performance Impact of Code and Data Placement on the IBM RP3 . Mats Brorssony Department of Computer Engineering Lund University P. O. Box 118 S-221 00 Lund, Sweden May 25, 1989
	ftp://dit.lth.se/pub/techreports/complete-papers/Dt-075.ps.Z, 19921210 Software Primitives for Emulation of Multiprocessor Architectures Anders Svensson Department of Computer Engineering, Lund University P.O. Box 118, S-221 00 Lund, Sweden
	ftp://dit.lth.se/pub/techreports/complete-papers/Dt-125.ps.Z, 19921210 1
	ftp://dit.lth.se/pub/techreports/complete-papers/Dt-066.ps.Z, 19921210 Optimization of finite state machines using subroutines Kenny Ranerup, and Lars Philipson Department of Computer Engineering, Lund University, Sweden
	ftp://dit.lth.se/pub/techreports/complete-papers/Dt-056.ps.Z, 19921210 A Decentralized Virtual Memory Scheme Implemented on an Emulated Multiprocessor Mats Brorsson Department of Computer Engineering, Lund University P.O. Box 118, S-221 00 Lund, Sweden
	ftp://dit.lth.se/pub/techreports/complete-papers/Dt-149.ps.Z, 19921210 The Scalable Tree Protocol { A Cache Coherence Approach for Large-Scale Multiprocessors H akan Nilsson and Per Stenstr om Department of Computer Engineering, Lund University P.O. Box 118, S-221 00 Lund, Sweden
	ftp://dit.lth.se/pub/techreports/complete-papers/Dt-074.ps.Z, 19921210 Basic Software for Virtual Memory Emulation on an Experimental Multiprocessor Anders Svensson Department of Computer Engineering, Lund University P.O. Box 118, S-221 00 Lund, Sweden
	ftp://dit.lth.se/pub/techreports/complete-papers/Dt-085.ps.Z, 19921210 A Simulation Model of a Highly Parallel MIMD Multiprocessor Fredrik Dahlgren Department of Computer Engineering Lund University P. O. Box 118, S-221 00 Lund Sweden e-mail: fredrik@dit.lth.se September 17, 1992 Thesis for the degree of Master of Science in Computer Science and Engineering.
	ftp://dit.lth.se/pub/techreports/complete-papers/Dt-097.ps.Z, 19921210 1
	ftp://dit.lth.se/pub/techreports/complete-papers/Dt-101.ps.Z, 19921210 1 Logic extraction from CMOS transistor networks Per Andersson and Kenny Ranerup, Department of Computer Engineering, Lund University, Sweden.
	ftp://dit.lth.se/pub/techreports/complete-papers/Dt-151.ps.Z, 19921210 Performance Evaluation of Link-Based Cache Coherence Schemes H akan Nilsson and Per Stenstr om Department of Computer Engineering, Lund University P.O. Box 118, S-221 00 Lund, Sweden
	ftp://dit.lth.se/pub/techreports/complete-papers/Dt-104.ps.Z, 19921210 A Program-driven Simulation Model of an MIMD Multiprocessor Fredrik Dahlgren Department of Computer Engineering, Lund University P.O. Box 118, S-221 00 Lund, Sweden
	ftp://dit.lth.se/pub/techreports/complete-papers/Dt-082.ps.Z, 19921210 History, an Intelligent Load Sharing Filter Anders Svensson Department of Computer Engineering, Lund University P.O. Box 118, S-221 00 Lund, Sweden
	ftp://dit.lth.se/pub/techreports/complete-papers/Dt-070.ps.Z, 19921210 Emulation of Shared Virtual Memory on an Experimental Multiprocessor. Mats Brorsson Department of Computer Engineering Lund University, Sweden October 16, 1989
	ftp://dit.lth.se/pub/techreports/complete-papers/Dt-116.ps.Z, 19921210 On Reconfigurable On-chip Data Caches Fredrik Dahlgren and Per Stenstr om Department of Computer Engineering, Lund University P.O. Box 118, S-221 00 Lund, Sweden
	ftp://dit.lth.se/pub/techreports/complete-papers/Dt-119.ps.Z, 19921210 Reducing Write Latencies for Shared Data in a Multiprocessor with a Multistage Network Fredrik Dahlgren and Per Stenstr om Department of Computer Engineering, Lund University P.O. Box 118, S-221 00 Lund, Sweden
	ftp://dit.lth.se/pub/techreports/complete-papers/Dt-083.ps.Z, 19921210 Emulation of Memory Structures on an Experimental Multiprocessor and Evaluation of some Load Sharing Algorithms. Anders Svensson Thesis for the degree of Teknisk Licentiat1 The papers summerized in this thesis are: 1. A. Svensson. Software Primitives for Emulation of Multiprocessor Architectures.
	ftp://dit.lth.se/pub/techreports/complete-papers/Dt-093.ps.Z, 19921210 1
	ftp://dit.lth.se/pub/techreports/complete-papers/Dt-124.ps.Z, 19921210 1
	ftp://dit.lth.se/pub/techreports/complete-papers/Dt-114.ps.Z, 19921210 4
	ftp://dit.lth.se/pub/techreports/complete-papers/Dt-081.ps.Z, 19921210 Dynamic Alternation between Receiver-Initiated and Sender-Initiated Load Sharing Anders Svensson Department of Computer Engineering, Lund University P.O. Box 118, S-221 00 Lund, Sweden Distributed adaptive load sharing can be of two basic types: either congested nodes take the initiative in
	ftp://dit.lth.se/pub/techreports/complete-papers/Dt-015.ps.Z, 19921214 Some experimental studies on implementation of parallel languages on multiprocessor computers by Anders Ard o Dissertation for the degree of Teknologie licenciat. The papers summarized in this thesis are: 1. A. Ard o, L. Philipson: `Implementation of a Pascal based parallel language on a multiprocessor
	ftp://dit.lth.se/pub/techreports/complete-papers/Dt-037.ps.Z, 19921214 Experience Acquiring and Retargeting a Portable Ada1 Compiler Anders Ard o Department of Computer Engineering University of Lund, P.O. Box 118 S-221 00 Lund, Sweden December 14, 1992 Keywords: Ada retargeting backend validation 1Ada is a registered trademark of the U.S. Government (Ada Joint Program
	ftp://dit.lth.se/pub/techreports/complete-papers/Dt-048.ps.Z, 19921214 Hardware support for efficient execution of AdaR tasking Anders Ard o Department of Computer Engineering, University of Lund P.O. Box 118, S-221 00 Lund, SWEDEN
	ftp://dit.lth.se/pub/techreports/complete-papers/Dt-064.ps.Z, 19921214 Design of a Microprocessor and its Software as a Seven Week Class Project Lars Philipson, Anders Ard o, and Kenny Ranerup Dept of Computer Engineering, Lund University P.O. Box 118, S-221 00 Lund, Sweden Phone: +46-46-107518, Email: lars@dit.lth.se
	ftp://dit.lth.se/pub/techreports/complete-papers/Dt-073.ps.Z, 19921214 The MUMS Multiprocessor Ada Project Anders Ard o and Lars Lundberg Department of Computer Engineering University of Lund, P.O. Box 118 S-221 00 Lund, Sweden 1 BACKGROUND Now, when the internal speed of computers is close to the physical limitations of electronic devices cf. parallelism is
	ftp://dit.lth.se/pub/techreports/complete-papers/Dt-033.ps.Z, 19921214 Efficiency Aspects on Ada Run Time Support for Multiprocessors with Shared Memory Anders Ard o Department of Computer Engineering University of Lund P.O. Box 118 S-221 00 Lund, Sweden Net address: BITNET: DDTNET@SELDC51 usenet: anders@perdix.lu.se or ...seismo!enea!agaton!perdix!anders December 14, 1992
	ftp://dit.lth.se/pub/techreports/complete-papers/Dt-084.ps.Z, 19921214 Design Principles for Shared Memory Multiprocessors A collection of papers from the MUMS project Edited by Lars Philipson, Anders Ard o, and Per Stenstr om Lund May, 1990 CONTENTS i CONTENTS Contents 1 Introduction 1 2 Initial studies 2 3 A layered experimental system 4 4 Virtual memory experiments 5 5
	ftp://dit.lth.se/pub/techreports/complete-papers/Dt-121.ps.Z, 19930204 A Latency-Hiding Scheme for Multiprocessors with Buffered Multistage Networks Per Stenstr om Department of Computer Engineering, Lund University P.O. Box 118, S-221 00 LUND, Sweden
	ftp://dit.lth.se/pub/techreports/complete-papers/Dt-111.ps.Z, 19930204 A Lockup-free Multiprocessor Cache Design Per Stenstr om, Fredrik Dahlgren, and Lars Lundberg Department of Computer Engineering, Lund University P.O. Box 118, S-221 00 LUND, Sweden
	ftp://dit.lth.se/pub/techreports/complete-papers/Dt-049.ps.Z, 19930204 VLSI Support for a Cactus Stack Oriented Memory Organization Per Stenstr om Department of Computer Engineering, University of Lund P.O. Box 118, S-221 00 Lund, Sweden
	ftp://dit.lth.se/pub/techreports/complete-papers/Dt-152.ps.Z, 19930204 Using Graphics and Animation to Visualize Instruction Pipelining and its Hazards Per Stenstr om, H akan Nilsson, and Jonas Skeppstedt Department of Computer Engineering, Lund University P.O. Box 118, S-221 00 LUND, Sweden
	ftp://dit.lth.se/pub/techreports/complete-papers/Dt-095.ps.Z, 19930218 Static Process Allocation Using Information about Program Behaviour Lars Lundberg Department of Computer Engineering, Lund University P.O. Box 118, S-221 00 Lund, Sweden
	ftp://dit.lth.se/pub/techreports/complete-papers/Dt-118.ps.Z, 19930302 Hardware Support for a Functionally-Programmed Tagged Token Architecture Jonas Alowersson and Glenn Jennings Department of Computer Engineering, Lund University P.O. Box 118, S-221 00 Lund, Sweden Tel. (+46)-46-1097 63, Fax (+46)-46-1047 14 Electronic Mail: glenn@dit.lth.se
	ftp://dit.lth.se/pub/techreports/complete-papers/Dt-147.ps.Z, 19930305
	ftp://dit.lth.se/pub/techreports/complete-papers/Dt-164.ps.Z, 19930811 I. Introduction Instruction level simulators are efficient tools for evaluating and debugging computer architectures. They are typically portable and highly flexible with respect to architectural modifications and instrumentation. However, a major problem arise when dealing with real application
	ftp://dit.lth.se/pub/techreports/complete-papers/Dt-150.ps.Z, 19931204 - 528 -
	ftp://dit.lth.se/pub/techreports/complete-papers/Dt-150-ext.ps.Z, 19931206 Visualising Sharing Behaviour in relation to Shared Memory Management 1 Visualising Sharing Behaviour in relation to Shared Memory Management MATS BRORSSON and PER STENSTR M Department of Computer Engineering, Lund University P.O. Box 118, S-221 00 LUND, Sweden email: matsbror@dit.lth.se tel:
	ftp://dit.lth.se/pub/techreports/complete-papers/Dt-172.ps.Z, 19940121 32 Visualisation of Cache Coherence Bottlenecks in Shared Memory Multiprocessor Applications Mats Brorsson and Per Stenstr m Department of Computer Engineering, Lund University, P.O. Box 118, S-221 00 Lund, Sweden email: matsbror@dit.lth.se
	ftp://dit.lth.se/pub/techreports/complete-papers/Dt-180.ps.Z, 19940413 Preliminary draft to appear, ICPP 94 An Integrated Methodology for the Verification of Directory-based Cache Protocols Fong Pong, Per Stenstr m* and Michel Dubois
	ftp://dit.lth.se/pub/techreports/complete-papers/Dt-176.ps.Z, 19940801 Simple Compiler Algorithms to Reduce Ownership Overhead in Cache Coherence Protocols Jonas Skeppstedt and Per Stenstr om Department of Computer Engineering, Lund University P.O. Box 118, S-221 00 Lund, SWEDEN
	ftp://dit.lth.se/pub/techreports/complete-papers/Dt-173.ps.Z, 19941116
	ftp://dit.lth.se/pub/techreports/complete-papers/Dt-183.ps.Z, 19941121 Jonas Alowersson and Per Andersson Department of Computer Engineering, Lund University, P.O. Box 118, S-221 00 Lund, Sweden Phone: +46 46 104940, Fax: +46 46 104714 email: jonasa@dit.lth.se, pera@dit.lth.se
	ftp://dit.lth.se/pub/techreports/complete-papers/Dt-158.ps.Z, 19941123
	ftp://dit.lth.se/pub/techreports/complete-papers/Dt-181.ps.Z, 19941123 This work was supported by the Swedish National Board for Technical Development (NUTEK) under the contract P855. Effectiveness of Hardware-Based Stride and Sequential Prefetching in Shared-Memory Multiprocessors Fredrik Dahlgren and Per Stenstr m Department of Computer Engineering, Lund University
	ftp://dit.lth.se/pub/techreports/complete-papers/Dt-159.ps.Z, 19941123 1 Using Write Caches to Improve Performance of Cache Coherence Protocols in Shared-Memory Multiprocessors Fredrik Dahlgren and Per Stenstr m Department of Computer Engineering, Lund University P.O. Box 118, S-221 00 LUND, Sweden
	ftp://dit.lth.se/pub/techreports/complete-papers/Dt-165.ps.Z, 19941123 1 Sequential Hardware Prefetching in Shared-Memory Multiprocessors Fredrik Dahlgren, Michel Dubois, and Per Stenstr m Department of Computer Engineering, Lund University P.O. Box 118, S-221 00 LUND, Sweden Department of Electrical Engineering-Systems University of Southern California Los Angeles,
	ftp://dit.lth.se/pub/techreports/complete-papers/Dt-189.ps.Z, 19941123 Using Hints to Reduce the Read Miss Penalty for Flat COMA Protocols* M rten Bj rkman, Fredrik Dahlgren, and Per Stenstr m Department of Computer Engineering, Lund University P.O. Box 118, S-221 00 LUND, Sweden locating a copy can include several directory lookups. This is in contrast to in CC-NUMA
	ftp://dit.lth.se/pub/techreports/complete-papers/Dt-166.ps.Z, 19941123 187 This work was partly supported by the Swedish National Board for Technical Development (NUTEK) under contract number 9001797 and by the National Science Foundation under Grant No. CCR-9115725. Combined Performance Gains of Simple Cache Protocol Extensions Fredrik Dahlgren, Michel Dubois, and Per
	ftp://dit.lth.se/pub/techreports/complete-papers/Dt-171.ps.Z, 19941123 This work was supported by the Swedish National Board for Technical Development (NUTEK), contract number 9001797. Reducing the Write Traffic for a Hybrid Cache Protocol Fredrik Dahlgren and Per Stenstr m Department of Computer Engineering, Lund University P.O. Box 118, S-221 00 LUND, Sweden access
	ftp://dit.lth.se/pub/techreports/complete-papers/Dt-145.ps.Z, 19941124 109
	ftp://dit.lth.se/pub/techreports/complete-papers/Dt-179.ps.Z, 19941124
	ftp://dit.lth.se/pub/techreports/complete-papers/Dt-117.ps.Z, 19941124 496
	ftp://dit.lth.se/pub/techreports/complete-papers/Dt-193.ps.Z, 19950303
	ftp://dit.lth.se/pub/techreports/complete-papers/Dt-204.ps.Z, 19950303 Dynamic CMOS Circuit Techniques for Delay and Power Reduction in Parallel Adders Hans Lindkvist and Per Andersson Department of Computer Engineering, Lund University, Sweden email: {hasse, pera}@dit.lth.se
	ftp://dit.lth.se/pub/techreports/complete-papers/Dt-205.ps.Z, 19950314
	ftp://dit.lth.se/pub/techreports/complete-papers/Dt-207.ps.Z, 19950323 A Compiler Algorithm that Reduces Read Latency in Ownership-Based Cache Coherence Protocols Jonas Skeppstedt and Per Stenstr om Department of Computer Engineering, Lund University P.O. Box 118, S-221 00 Lund, SWEDEN Internet: fjonass,perg@dit.lth.se, http://www.dit.lth.se/cachemire/
	ftp://dit.lth.se/pub/techreports/complete-papers/Dt-192.ps.Z, 19950609 178
	ftp://dit.lth.se/pub/techreports/complete-papers/Dt-189.USletter.ps.Z, 19950612 Using Hints to Reduce the Read Miss Penalty for Flat COMA Protocols* M rten Bj rkman, Fredrik Dahlgren, and Per Stenstr m Department of Computer Engineering, Lund University P.O. Box 118, S-221 00 LUND, Sweden locating a copy can include several directory lookups. This is in contrast to in CC-NUMA
	ftp://dit.lth.se/pub/techreports/complete-papers/Dt-205.USletter.ps.Z, 19950612
	ftp://dit.lth.se/pub/techreports/complete-papers/Dt-171.USletter.ps.Z, 19950612 This work was supported by the Swedish National Board for Technical Development (NUTEK), contract number 9001797. Reducing the Write Traffic for a Hybrid Cache Protocol Fredrik Dahlgren and Per Stenstr m Department of Computer Engineering, Lund University P.O. Box 118, S-221 00 LUND, Sweden access
	ftp://dit.lth.se/pub/techreports/complete-papers/Dt-181.USletter.ps.Z, 19950612 This work was supported by the Swedish National Board for Technical Development (NUTEK) under the contract P855. Effectiveness of Hardware-Based Stride and Sequential Prefetching in Shared-Memory Multiprocessors Fredrik Dahlgren and Per Stenstr m Department of Computer Engineering, Lund University
	ftp://dit.lth.se/pub/techreports/complete-papers/Dt-189.A4.ps.Z, 19950612 Using Hints to Reduce the Read Miss Penalty for Flat COMA Protocols* M rten Bj rkman, Fredrik Dahlgren, and Per Stenstr m Department of Computer Engineering, Lund University P.O. Box 118, S-221 00 LUND, Sweden locating a copy can include several directory lookups. This is in contrast to in CC-NUMA
	ftp://dit.lth.se/pub/techreports/complete-papers/Dt-171.A4.ps.Z, 19950612 This work was supported by the Swedish National Board for Technical Development (NUTEK), contract number 9001797. Reducing the Write Traffic for a Hybrid Cache Protocol Fredrik Dahlgren and Per Stenstr m Department of Computer Engineering, Lund University P.O. Box 118, S-221 00 LUND, Sweden access
	ftp://dit.lth.se/pub/techreports/complete-papers/Dt-166.USletter.ps.Z, 19950612 This work was partly supported by the Swedish National Board for Technical Development (NUTEK) under contract number 9001797 and by the National Science Foundation under Grant No. CCR-9115725. Combined Performance Gains of Simple Cache Protocol Extensions Fredrik Dahlgren, Michel Dubois, and Per Stenstr
	ftp://dit.lth.se/pub/techreports/complete-papers/Dt-166.A4.ps.Z, 19950612 This work was partly supported by the Swedish National Board for Technical Development (NUTEK) under contract number 9001797 and by the National Science Foundation under Grant No. CCR-9115725. Combined Performance Gains of Simple Cache Protocol Extensions Fredrik Dahlgren, Michel Dubois, and Per Stenstr
	ftp://dit.lth.se/pub/techreports/complete-papers/Dt-205.A4.ps.Z, 19950612
	ftp://dit.lth.se/pub/techreports/complete-papers/Dt-181.A4.ps.Z, 19950612 This work was supported by the Swedish National Board for Technical Development (NUTEK) under the contract P855. Effectiveness of Hardware-Based Stride and Sequential Prefetching in Shared-Memory Multiprocessors Fredrik Dahlgren and Per Stenstr m Department of Computer Engineering, Lund University
	ftp://dit.lth.se/pub/techreports/complete-papers/Dt-158.A4.ps.Z, 19950612
	ftp://dit.lth.se/pub/techreports/complete-papers/Dt-158.USletter.ps.Z, 19950612
	ftp://dit.lth.se/pub/techreports/complete-papers/Dt-208.USletter.ps.Z, 19950727 Effectiveness of Hardware-Based and Compiler-Controlled Snooping Cache Protocol Extensions Fredrik Dahlgren, Jonas Skeppstedt, and Per Stenstr m Department of Computer Engineering, Lund University P.O. Box 118, S-221 00 LUND, Sweden Internet: fredrik@dit.lth.se, http://www.dit.lth.se/cachemire/
	ftp://dit.lth.se/pub/techreports/complete-papers/Dt-208.A4.ps.Z, 19950727 Effectiveness of Hardware-Based and Compiler-Controlled Snooping Cache Protocol Extensions Fredrik Dahlgren, Jonas Skeppstedt, and Per Stenstr m Department of Computer Engineering, Lund University P.O. Box 118, S-221 00 LUND, Sweden Internet: fredrik@dit.lth.se, http://www.dit.lth.se/cachemire/