Cache Design for High Performance Graphics Architectures 1

CERC Technical Report Series

Research Note

CERC-TR-RN-96-005

CACHE DESIGN FOR HIGH PERFORMANCE

GRAPHICS ARCHITECTURES

Srinivas Kankanahalli

Raghu Karinthi

Rahul Jain

1996

ACKNOWLEDGEMENT: This effort was sponsored by the Defense Advanced Research Projects Agency (DARPA), under Grant No. MDA972-91-J-1022 for the DARPA Initiative in Concurrent Engineering (DICE) and by NASA under Grant Number NAG 5-2129.

Concurrent Engineering Research Center

West Virginia University

P. O. Box 6506, Morgantown WV 26506

Cache Design for High Performance Graphics Architectures 2

Cache Design for High Performance Graphics Architectures

Srinivas Kankanahalli, Raghu Karinthi and Rahul Jain
West Virginia University, Morgantown, WV 26506
{sriniv,raghu,rahul}@cerc.wvu.edu

Abstract

With the increase in disparity between the CPU speeds and the memory access speeds, caches play a very significant role in the overall performance of the system. 3D-graphics rendering applications are very CPU intensive and have always pushed the systems to its limits. The last step in the 3D graphics rendering pipeline is scan-conversion, where intermediate pixel positions and colors are calculated by interpolation and written to the framebuffer. Access to the framebuffer is limited by memory access speeds. We believe that by providing a dedicated cache for the framebuffer memory we should be able to speed up the process. The aim of this work was to study the cache design issues and determine the optimal cache design for scan conversion based on cache simulations.