Caches: A Review 1

CERC Technical Report Series

Research Note

CERC-TR-RN-96-006

CACHES: A REVIEW

Srinivas Kankanahalli

Raghu Karinthi

Rahul Jain

1996

ACKNOWLEDGEMENT: This effort was sponsored by the Defense Advanced Research Projects Agency (DARPA), under Grant No. MDA972-91-J-1022 for the DARPA Initiative in Concurrent Engineering (DICE) and by NASA Grant Number NAG 5-2129.

Concurrent Engineering Research Center

West Virginia University

P. O. Box 6506, Morgantown WV 26506

Caches: A Review 2

Caches: A Review

Srinivas Kankanahalli, Raghu Karinthi and Rahul Jain
West Virginia University, Morgantown, WV 26506
{sriniv,raghu,rahul}@cerc.wvu.edu

Abstract

There is great disparity between the rate at which CPU speeds are increasing as compared to the rate at which memory can be accessed. The CPU often has to stall, waiting for words from the memory. Caches help alleviate this problem, and their design is very critical to the overall system performance. This paper presents the definitions of terms and concepts related to caches. It also presents the steps involved in using the cache profiling and cache simulation tools comprising the Wisconsin Architectural Research Tool Set (WARTS), which have been developed at the Computer Sciences Department, University of Wisconsin, Madison.

1 Introduction

Today, the rate at which CPU speeds are increasing is much higher than the rate at which memory can be accessed. Because of this difference in speeds, the CPU often has to stall and wait for words from the memory. Caches help alleviate this problem and their design is very critical to the overall system performance. While studying the various papers on cache design we did not find a consistent use of terms and definitions. We present our understanding of the definitions below, which to us conveyed the intent more clearly than others. The major portion of our reading is based on [5].