RTBA : A Generic Bit-Sliced Bus Architecture for

DataPath Synthesis?

Kamlesh Rath

Ignacio Celis

Robert M. Wehrmeister

Steven D. Johnson

Computer Science Department

Indiana University, Bloomington, IN 47405

Abstract

Register transfer level (RTL) equations are used to specify the register and ALU datapaths

of machine architectures. RTBA (Register Transfer Bus Architecture) is a target architecture

for automatic bit-sliced VLSI implementation of RTL equations. This article discusses the

automatic derivation process of a layout from a typical system of RTL equations using a series

of behavior preserving transformations. The test results of a chip fabricated using the derived

layout are also presented. Extensions to the RTBA transformations, allowing functions in the

RTL equations, are presented by deriving the min-max benchmark.

?This research was supported in part by the National Science Foundation under grants numbered MIP 8707067,

MIP 8921842, and DCR 8521497.