A Futurebus interface from off-the-shelf parts
Simon L Peyton Jones
Department of Computing Science, University of Glasgow, G12 8QQ
(email: [email protected])
Department of Computer Science, University College London
June 22, 1990
As part of the GRIP project we have designed a Futurebus interface using off-the-shelf parts. We describe our implementation, which is unusual in its use of fully asynchronous finite state machines. Based on this experience we draw some lessons for designers using Futurebus.
As part of our implementation of the GRIP multiprocessor (Peyton Jones et al. ) we have designed a bus-based subsystem to interconnect a number of homogenous modules. An introduction to GRIP is given in Section 2.
For reasons discussed later, we based the communications subsystem on the (then) draft IEEE P896 Futurebus standard. The unusual feature of the Futurebus protocols is that they are entirely asynchronous; there is no global clock, and all transactions proceed correctly at the speed of the slowest participating module. Futurebus has been the subject of several previous papers in IEEE Micro (Balakrishnan ; Taub ; Taub ). An introduction to Futurebus is given in Section 3.
The purpose of this paper is to describe the practical aspects of the design of our Futurebus interface, paying particular attention to the asynchronous parts, which distinguish it from other bus interfaces. For several reasons, our design does not conform to the current Futurebus standard:
ffl Our primary objective was to achieve high-bandwidth communication between homogeneous boards, at minimum cost in printed circuit board real estate, and without using custom VLSI. It was clearly not possible to implement the full Futurebus protocols (which are quite elaborate) using this technology, so we chose a small subset that was adequate for our needs.
ffl In a number of places strict adherence to the draft standard we were using would have had a substantial cost in real estate or speed. Since we were not anticipating interworking with