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CSRD Report No. 1189 Center for Supercomputing Research and Development Life Span Strategy { A Compiler-Based Approach to Cache Coherence by Hoichi Cheong University of Illinois at Urbana-Champaign 104 S. Wright Street Urbana, Illinois 61801 (217) 333 6233 Copyright 1992, Board of Trustees of the
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Performance Analysis of Parallelizing Compilers on the Perfect BenchmarksTM Programs William Blume and Rudolf Eigenmann Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign Urbana, Illinois 61801
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The Impact of Wiring Constraints on Hierarchical Network Performance William Tsun-yuk Hsu Pen-Chung Yew Center for Supercomputing Research and Development 305 Talbot Labs, 104 S. Wright, Urbana IL 61801, USA
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ON THE PARALLEL SOLUTION OF PARABOLIC EQUATIONS E. GALLOPOULOS Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign Urbana, Illinois 61801 stratis@uicsrd.csrd.uiuc.edu Y. SAAD RIACS, Mail Stop 230-5 NASA Ames Research Center Moffet Field, California 94035
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PARCEL and MIPRAC: Parallelizers for Symbolic and Numeric Programs Williams Ludwell Harrison III and Zahira Ammarguellat May 7, 1992 1 Introduction PARCEL is a compiler and run-time system that automatically parallelizes a Scheme program for execution on a shared-memory multiprocessor; it is described
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Experiments in Thermal Hydraulics Simulation: Multiprocessing COMMIX S. Aslamy E. Gallopoulosy M. Hamy T. Canfieldz M. Minkoffz R. Blomquistz October 24, 1991
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EFFICIENT PARALLEL SOLUTION OF PARABOLIC EQUATIONS: IMPLICIT METHODS ON THE CEDAR MULTICLUSTER E. GALLOPOULOS AND Y. SAADy
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A MEMORY-CONSERVING HYBRID METHOD FOR SOLVING LINEAR SYSTEMS WITH MULTIPLE RIGHT HAND SIDES V. SIMONCINI AND E. GALLOPOULOSy
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Experiments with an Ocean Circulation Model on CEDAR L. DeRose, K. Gallivan, E. Gallopoulos Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign Urbana, Illinois 61801 U.S.A.
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Parallel ocean circulation modeling on Cedar L. DeRosey K. Gallivany E. Gallopoulosyz A. Navarrax May 1991
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The Design of Automatic Parallelizers for Symbolic and Numeric Programs Williams Ludwell Harrison III and Zahira Ammarguellat May 7, 1992 1 Introduction Parcel is a compiler and run-time system that automatically parallelizes a Scheme program for execution on a shared-memory multiprocessor; it is
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EFFICIENT SOLUTION OF PARABOLIC EQUATIONS BY KRYLOV APPROXIMATION METHODS E. GALLOPOULOS AND Y. SAAD y
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PTOPP - A PRACTICAL TOOLSET FOR THE OPTIMIZATION OF PARALLEL PROGRAMS BY PATRICK EARL MCCLAUGHRY B.S., University of Illinois at Urbana-Champaign, 1990 THESIS Submitted in partial fulfillment of the requirements for the degree of Master of Science in Computer Science in the Graduate College of the
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Perfect BenchmarksTM: Instrumented Version Priyamvada Sinvhal-Sharma, Lawrence Rauchwerger and John Larson September 5, 1991 1 Introduction Application-based benchmarks such as the Perfect Benchmark suite have gained significant acceptance and are being used as a sample of real world scientific
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In 1992 Intl Conference on Parallel Processing, August 1992, St. Charles, IL EFFICIENT RACE CONDITION DETECTION FOR SHARED-MEMORY PROGRAMS WITH POST/WAIT SYNCHRONIZATION Robert H.B. Netzer Sanjoy Ghosh Computer Sciences Department CSRD University of Wisconsin-Madison 305 Talbot Lab 1210 W. Dayton Street
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A General Framework for Analyzing Shared-Memory Parallel Programs Jyh-Herng Chow and Williams Ludwell Harrison III Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign Urbana, IL 61801
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MaxPar Extensions for Isolating Performance Problems Samuel Ho Center for Supercomputing Research and Development University of Illinois, Urbana, Illinois 61801
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CSRD report no. 1179 Center for Supercomputing Research and Development hhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhh Performance Evaluation of Wire-limited Hierarchical Networks William Tsun-yuk Hsu and Pen-chung Yew August 3, 1992
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Restructuring Fortran Programs for Cedar Rudolf Eigenmann, Jay Hoeflinger, Greg Jaxon, Zhiyuan Li, David Padua Center for Supercomputing Research & Development University of Illinois at Urbana-Champaign Urbana, Illinois 61801
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Experience in the Automatic Parallelization of Four Perfect-Benchmark Programs Rudolf Eigenmann, Jay Hoeflinger, Zhiyuan Li, and David Padua Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign Urbana, Illinois
open this document and view contentsftp://sp2.csrd.uiuc.edu/pub/CSRD_Reports/reports/1237.ps.gz, 19921020
Symbolic Program Analysis and Optimization for Parallelizing Compilers Mohammad R. Haghighat Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign Urbana, IL 61801-2932 Constantine D. Polychronopoulos Kubota Pacific Computer Inc. 2630 Walsh Avenue Santa Clara, CA
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Interprocedural Data Flow Analysis for Compile-time Memory Management Kwangkeun Yi and Williams Ludwell Harrison III @csrd.uiuc.edu Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign
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Dynamic Dependence Analysis: A Novel Method for Data Dependence Evaluation Paul M. Petersen David A. Padua Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign Urbana, IL, 61801-2932 fpetersen,paduag@csrd.uiuc.edu
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Machine-Independent Evaluation of Parallelizing Compilers Paul M. Petersen and David A. Padua
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SUCCESS AND LIMITATIONS IN AUTOMATIC PARALLELIZATION OF THE PERFECT BENCHMARKSTM PROGRAMS BY WILLIAM JOSEPH BLUME B.S., University of Illinois, 1989 THESIS Submitted in partial fulfillment of the requirements for the degree of Master of Science in Computer Science in the Graduate College of the
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Multiple Omega Networks for Parallel Processing 1 Jos e Eduardo Moreira moreira@csrd.uiuc.edu Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign 465 CSRL, 1308W Main St Urbana, IL 61801 phone: 217{244{0049 fax: 217{244{1351 To be presented at the IV Brazilian
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Automatic Generation and Management of Interprocedural Program Analyses Kwangkeun Yi and Williams Ludwell Harrison III (kwang|harrison)@csrd.uiuc.edu Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign 465 CSRL, 1308 West Main St., Urbana, IL 61801-2307
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1 CHAPTER 1 INTRODUCTION 1.1. Context The interconnection network is a crucial component of a large-scale multiprocessor system. In shared-memory machines, the network provides processors with access to memory modules. In distributed-memory machines, the network provides connections for processors to
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Estimating the Inherent Parallelism in Prolog Programs David C. Sehr Laxmikant V. Kal e y University of Illinois at Urbana-Champaign
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Efficient Computation of Fixpoints that Arise in Complex Program Analysis Li-Ling Chen and Williams Ludwell Harrison III @csrd.uiuc.edu Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign 1308 West Main Street, Urbana, IL 61801
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AUTOMATIC DETECTION OF NONDETERMINACY, AND SCALAR OPTIMIZATIONS IN PARALLEL PROGRAMS BY SANJOY GHOSH B.Engg., Birla Institute of Technology and Science, 1982 M.Tech., Indian Institute of Technology, 1986 THESIS Submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy
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Microarchitecture Support for Dynamic Scheduling of Acyclic Task Graphs 1 Carl J. Beckmann beckmann@csrd.uiuc.edu Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign 305 Talbot Lab, 104 S. Wright St. Urbana, IL. 61801 tel. 217-244-0052 Constantine D.
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Practical Tools for Optimizing Parallel Programs Rudolf Eigenmann Patrick McClaughry Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign
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Detecting Redundant Accesses to Array Data (Extended Version) Elana D. Granston y High Performance Computing Division Department of Computer Science Leiden University Niels Bohrweg 1, 2333 CA Leiden, The Netherlands Alexander V. Veidenbaumz Center for Supercomputing Research and Development University
open this document and view contentsftp://sp2.csrd.uiuc.edu/pub/CSRD_Reports/reports/1267.ps.gz, 19930105
Compile Time Techniques for Using the Priority Data Cache to Reduce Memory Access Delays Elana D. Granston y High Performance Computing Division Department of Computer Science Leiden University Niels Bohrweg 1, 2333 CA Leiden, The Netherlands granston@cs.LeidenUniv.nl Alexander V. Veidenbaumz Center for
open this document and view contentsftp://sp2.csrd.uiuc.edu/pub/CSRD_Reports/reports/1279.ps.gz, 19930106
EVALUATION OF PARALLELIZING COMPILERS David A. Padua and Paul M. Petersen Center for Supercomputing Research and Development University of Illinois at Champaign-Urbana Urbana, Illinois, 61801, U.S.A.
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Interactive Steering Using the Application Executive Brian Bliss Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign Urbana, Illinois 61801 1
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INSTRUMENTATION OF FORTRAN PROGRAMS FOR AUTOMATIC ROUNDOFF ERROR ANALYSIS AND PERFORMANCE EVALUATION BY BRIAN EUGENE BLISS B.S., University of Illinois, 1987 THESIS Submitted in partial fulfillment of the requirements for the degree of Master of Science in Computer Science in the Graduate College of the
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System Z1 Programming Manual1 Kwangkeun Yi and Luddy Harrison Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign 465 CSRL, 1308 West Main Street Urbana, IL 61801-2307 January 1993 1This work was supported in part by the U.S. Department of Energy under Grant No.
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MDB - A Parallel Debugger for Cedar Perry Emrath Bret Marsolf emrath@csrd.uiuc.edu marsolf@csrd.uiuc.edu Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign 104 S. Wright, Urbana, Illinois 61801 Mdb is a parallel debugger that was developed for debugging
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The Cedar System and an Initial Performance Study D. Kuck, E. Davidsony, D. Lawrie y, A. Sameh C.-Q Zhuy, A. Veidenbaum, J. Konicek, P. Yew, K. Gallivan, W. Jalbyy, H. Wijshoffy, R. Bramleyy, U.M. Yang P. Emrath, D. Padua, R. Eigenmann, J. Hoeflinger, G. Jaxony, Z. Liy, T. Murphy, J. Andrews, S. Turner
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USING A CACHE IN PLACE OF A CEDAR-LIKE VECTOR PREFETCH UNIT BY MAHDI SEDDIGHNEZHAD B.Engr., Shiraz University, 1986 THESIS Submitted in partial fulfillment of the requirements for the degree of Master of Science in Computer Science in the Graduate College of the University of Illinois at
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Toward a Methodology of Optimizing Programs for High-Performance Computers Rudolf Eigenmann for Supercomputing Research and Development (CSRD) University of Illinois at Urbana-Champaign, USA
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Original Loop Bounds Loop Bounds Assumed Constant Type Count (%) Count (%) Difference Proved Dependent Constant Test 116616 26.7% 116616 26.7% 0.0% Integer Programming 1553 0.4% 30697 7.0% 6.6% Omega Test 70770 16.2% 39684 9.1% -7.1% Total Proved Dependent 188939 43.3% 186997 42.9% -0.4% Assumed
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EVALUATION OF PROGRAMS AND PARALLELIZING COMPILERS USING DYNAMIC ANALYSIS TECHNIQUES BY PAUL MARX PETERSEN B.S., University of Nebraska{Lincoln, 1986 M.S., University of Illinois at Urbana{Champaign, 1989 THESIS Submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy
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Generalized Iteration Space and the Parallelization of Symbolic Programs (Extended Abstract) Luddy Harrison October 15, 1991
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Cedar Fortran Programmer's Manual 1 Jay Hoeflinger Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign Urbana, Illinois 61801 June 14, 1993 1This work was supported by the U.S. Department of Energy under Grant No. DOE DE- FG02-85ER25001. Contents 1 Introduction
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Polaris: A New-Generation Parallelizing Compiler for MPPs R & D Status Report June 15, 1993 David A. Padua Rudolf Eigenmann Jay Hoeflinger Paul Petersen Peng Tu Stephen Weatherford Keith Faigin Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign. CSRD Report No.
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In Proc. Sixth SIAM Conf. Parallel Processing for Scientific Computing, R. F. Sincovec et al. eds., pp. 652-655, SIAM, Philadelphia, March 1993. Accuracy Control for Parallel Evaluation of Matrix Rational Functions D. Calvettiy, E. Gallopoulos and L. Reichelz January 1993 CSRD Report No. 1278 Center for
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EFFICIENT SOLUTION OF LARGE SPARSE EIGENVALUE PROBLEMS IN MICROELECTRONIC SIMULATION BY ALBERT THOMAS GALICK B.S., Massachusetts Institute of Technology, 1980 M.S., University of Illinois, 1984 THESIS Submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Computer
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To appear in SIAM J. Scientific Computing. A Quasi-Minimal Residual Variant of the Bi-CGStab Algorithm for Nonsymmetric Systems T. F. Chany, E. Gallopoulos , V. Simoncini , T. Szetoy and C. H. Tongz February 1993 (revised) CSRD Report No. 1231 y Dept. of Mathematics University of California - Los
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To appear in Parallel Supercomputing in Atmospheric Science, G.-R. Hoffmann and T. Kauranne eds., World Scientific, 1993. Paper from Fifth ECMWF Workshop on Use of Multiprocessors in Meteorology, European Centre for Medium Range Weather Forecasts, Nov. 1992. Status Report: Parallel Ocean Circulation on
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Automatic Generation and Management of Program Analyses Kwangkeun Yi Department of Computer Science Center for Supercomputing Research and Development1 THESIS Submitted in partial fulfillment of the requirements for the degree of Doctor of Philosphy in Computer Science in the Graduate College of the
open this document and view contentsftp://sp2.csrd.uiuc.edu/pub/CSRD_Reports/reports/1314.ps.gz, 19931001
Symbolic Analysis: A Basis for Parallelization, Optimization, and Scheduling of Programs Mohammad R. Haghighat Constantine D. Polychronopoulos Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign Urbana, IL 61801-2932
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Redundant Synchronization Elimination for DOACROSS Loops Ding-Kai Chen Pen-Chung Yew fdkchen,yewg@csrd.uiuc.edu Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign Urbana, Illinois, 61820 December 8, 1993
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Automatic Array Privatization Peng Tu and David Padua Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign
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Supercomputer Performance Evaluation and the Perfect BenchmarksTM George Cybenko Lyle Kipp Lynn Pointer David Kuck May 21, 1993
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Automatic Program Parallelization Utpal Banerjee Intel Corporationy Rudolf Eigenmann University of Illinois at Urbana-Champaign Alexandru Nicolau University of California at Irvine David A. Padua University of Illinois at Urbana-Champaign February 1993
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The Polaris Internal Representation1 Keith A. Faigin Jay P. Hoeflinger David A. Padua Paul M. Petersen Stephen A. Weatherford February 18, 1994 Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign Urbana, Illinois, 61801
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NOTIFICATION AND MULTICAST NETWORKS FOR SYNCHRONIZATION AND COHERENCE* by John B. Andrews Carl J. Beckmann David K. Poulsen Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign Urbana, Illinois 61801
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A Control-Flow Normalization Algorithm and Its Complexity Zahira Ammarguellat Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign Urbana, Illinois, 61801 July 17, 1992
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A Program's Eye View of Miprac Williams Ludwell Harrison, III Zahira Ammarguellat Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign Urbana, Illinois, 61801 (harrisonjammargue)@csrd.uiuc.edu May 18, 1992
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Parallelization of WHAMS3D on Two Shared-Memory Multiprocessors H.-C. Chen y H. Gaoz G. Laix April 21, 1994 1 Introduction The third phase of the WHAMS3D project has been completed. The main tasks during this phase were the parallelization of the code on both the Cray Y-MP4/464 and the Alliant FX/80
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INTERACTIVE DIRECT VOLUME RENDERING OF CURVILINEAR AND UNSTRUCTURED DATA BY PETER LAWRENCE WILLIAMS B.S., University of California, Berkeley, 1960 M.S., University of Lowell, 1984 THESIS Submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Computer Science in
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PRECONDITIONED CONJUGATE GRADIENT SCHEMES FOR HIERARCHICAL PARALLEL ARCHITECTURES ULRIKE MEIER YANG
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Analysis and Exploration of the program FALSE Grant Haab UIUC CRHC and ECE Department Michael Klemme Universit at | Gesamthochschule | Paderborn Sharad Mehrotra UIUC Center for Supercomputing R & D and CS Department Krishna Subramanian SunPro, A Sun Microsystems Inc. Businessy September 1992
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AN ORTHOGONAL PROJECTION ALGORITHM FOR LINEAR STOKES PROBLEMS R. BRAMLEY CENTER FOR SUPERCOMPUTING RESEARCH AND DEVELOPMENT UNIVERSITY OF ILLINOIS - URBANA
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Tools That Led To Increased Program Performance Patrick McClaughry and Rudolf Eigenmann CSRD Report 1184 January 1992
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Design Issues and Their Performance Impact in Systems with Directory-Based Caches Yung-Chin Chen Alexander V. Veidenbaum Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign
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c Copyright by Sirpa Helena Saarinen 1994 MODELLING FUNCTIONS FROM SAMPLE DATA WITH CLASSIFICATION APPLICATIONS BY SIRPA HELENA SAARINEN Lic., Turun Yliopisto, 1984 M.S., University of Cambridge, 1988 THESIS Submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy in
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The Importance of Prepass Code Scheduling for Superscalar and Superpipelined Processors Pohua P. Chang Daniel M. Lavery Scott A. Mahlke William Y. Chen Wen-mei W. Hwu March 8, 1994
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Run-time Visualization of Program Data Allan Tuchman, David Jablonowski, and George Cybenko Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign Urbana, Illinois 61801 ftuchman,davej,gcg@uicsrd.csrd.uiuc.edu
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Algorithms and Applications Research at CSRD E. Gallopoulos Center for Supercomputing Research and Development University of Illinois at Urbana Champaign Urbana, Illinois 61801 1 Introduction The Center for Supercomputing Research and Development was established at the University if Illinois in late
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Iterative Solution of the Eigenvalue Problem for a Dielectric Waveguide Albert T. Galick, Center for Supercomputing Research and Development, University of Illinois at Urbana{Champaign, Urbana, IL 61801, Thomas Kerkhoven, Department of Computer Science and Department of Electrical and Computer
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BEWARE OF UNPERTURBED MODIFIED INCOMPLETE FACTORIZATIONS VICTOR EIJKHOUTy
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A Collection of Codes for Sparse Matrix Computations U. Meier G. Skinner J. Gunnels July 1991
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VISTA: A SYSTEM FOR REMOTE DATA VISUALIZATION ALLAN TUCHMAN, GEORGE CYBENKO, DAVID JABLONOWSKI, BRIAN BLISS, SANJAY SHARMA y
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Synchronous Parallel Discrete Event Simulation on Shared-Memory Multiprocessors Pavlos Konas and Pen-Chung Yew Center for Supercomputing Research and Development, 305 Talbot Laboratory, 104 S. Wright Street, Urbana, IL 61801.
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Abridged version in International Conference on Parallel Processing , August, 1991. An Integrated Hardware/Software Solution for Effective Management of Local Storage in High-Performance Systems (Extended Version) Elana D. Granston Alexander V. Veidenbaum Center for Supercomputing Research and
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Documentation and Cedar Experiments for FLO52 K. A. Gallivan and U. Meier Yang May 31, 1994 1 Introduction This document consists of two major portions. The first part (Sections 1 through 7) provides detailed information concerning the overall execution of the code flo52 and the functions of the major
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An Analysis of a Cedar Implementation of dyfesm U. Meier Yang K. A. Gallivan 1 Introduction In the context of parallel processing and performance evaluation it is important to consider the performance of codes more complex than basic subroutines. The Perfect benchmark suite is one attempt to provide
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CIMGS: An Incomplete Orthogonal Factorization Preconditioner Xiaoge Wang Department of Computer Science Indiana University - Bloomington Kyle A. Gallivan Department of Electrical and Computer Engineering University of Illinois at Urbana-Champaign Randall Bramley Department of Computer Science Indiana
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MULTIPROCESSOR SPARSE SVD ALGORITHMS AND APPLICATIONS BY MICHAEL WAITSEL BERRY B.S., University of Georgia, 1981 M.S., North Carolina State University, 1983 THESIS Submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Computer Science in the Graduate College of
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BEWARE OF UNPERTURBED MODIFIED INCOMPLETE FACTORIZATIONS VICTOR EIJKHOUTy
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Experimental Evaluation of Some Data Dependence Tests (Extended Abstract) Paul M. Petersen and David A. Padua Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign Urbana, Illinois, 61801 1 Introduction Data dependence analysis is the most important step in the
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Analysis of Parallel Incomplete Point Factorizations Victor Eijkhout Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign 305 Talbot Laboratory, 104 South Wright street, Urbana, Illinois 61801-2932, USA
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A System for Remote Data Visualization Allan Tuchman, David Jablonowski, and George Cybenko Center for Supercomputing Research and Development 305 Talbot Lab University of Illinois Urbana, Illinois 61801 tuchman@uicsrd.csrd.uiuc.edu davej@uicsrd.csrd.uiuc.edu gc@uicsrd.csrd.uiuc.edu
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LARGE GRAIN PARALLEL SPARSE SYSTEM SOLVER BY BRET ANDREW MARSOLF B.S.C.S., Rose-Hulman Institute of Technology, 1987 THESIS Submitted in partial fulfillment of the requirements for the degree of Master of Science in Computer Science in the Graduate College of the University of Illinois at
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1 1 Automatic Parallelization and Manual Improvements of the Perfect Club Program OCEAN for Cedar Jay Hoeflinger July, 1992 Contents 1 Overall results 3 2 Discussion of the most important loops 3 2.1 The Group 1 Loops : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 3 2.2
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1 1 Automatic Parallelization and Manual Improvements of the Perfect Club Program TRFD for Cedar Jay Hoeflinger July, 1992 Contents 1 Overall results 3 2 Discussion of the Major Loops 3 2.1 TRFD do30 : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 3 2.2 OLDA do100
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1 1 Automatic Parallelization and Manual Improvements of the Perfect Club Program QCD for Cedar Jay Hoeflinger July 1992 Contents 1 Overall results 3 2 About the three versions of the code 4 3 Discussion of the most important loops 4 3.1 The Outer Loops : : : : : : : : : : : : : : : : : : : : : : : : :
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A Control-Flow Normalization Algorithm and Its Complexity Zahira Ammarguellat Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign Urbana, Illinois, 61801 July 17, 1992
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Run-Time Dependence Testing by Integer Sequence Analysis Jay Hoeflinger Center for Supercomputing Research & Development University of Illinois at Urbana-Champaign Urbana, Illinois 61801 January, 1992
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ISSUES ON THE DESIGN OF PARALLELIZING COMPILERS BY BRUCE PAUL LEUNG B.S., Purdue University, 1986 THESIS Submitted in partial fulfillment of the requirements for the degree of Master of Science in Computer Science in the Graduate College of the University of Illinois at Urbana-Champaign, 1990 Urbana,
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A Polygonal Approximation to Direct Scalar Volume Rendering Peter Shirley Allan Tuchmany Center for Supercomputing Research and Development 305 Talbot Lab University of Illinois Urbana, Illinois 61801
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AN OVERVIEW OF INTERPROCEDURAL ANALYSIS TECHNIQUES FOR HIGH PERFORMANCE PARALLELIZING COMPILERS BY DALE ALLAN SCHOUTEN B.S., University of Arizona, 1986 THESIS Submitted in partial fulfillment of the requirements for the degree of Master of Science in Computer Science in the Graduate College of the
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VASE User's Manual Version 1.0 David Jablonowski Brian Bliss John Bruner Robert Haber June 15, 1994 1 Contents 1 VASE Overview 4 2 System Requirements 7 3 Creating a VASE Application 8 3.1 Introduction and Setup : : : : : : : : : : : : : : : : : : : : : 8 3.2 Annotating the Original Source Code : : : :
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FINDING AND EXPLOITING PARALLELISM IN A PRODUCTION COMBUSTION SIMULATION PROGRAM BY GREGG MACLEAN SKINNER B.A., Goshen College, 1990 THESIS Submitted in partial fulfillment of the requirements for the degree of Master of Science in Computer Science in the Graduate College of the University of Illinois
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Simulation of DNA Solvation on a Shared-Memory Parallel Computer Gregg M. Skinner March 1992
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ACKNOWLEDGMENT I would like to express my deep gratitude to my advisor, Dr. Williams Ludwell Harrison III, who guided and always encouraged me with patience and insight throughout this work. I am appreciated, in addition, for his understanding of my many strange manners originated from my second
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COMPILE-TIME ANALYSIS OF EXPLICITLY PARALLEL PROGRAMS BY JYH-HERNG CHOW B.S., National Taiwan University, 1985 M.S., University of Illinois at Urbana-Champaign, 1990 THESIS Submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Computer Science in the Graduate
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HARDWARE AND SOFTWARE FOR FUNCTIONAL AND FINE GRAIN PARALLELISM BY CARL JOSEF BECKMANN B.S., Brown University, 1984 M.S., University of Illinois, 1989 THESIS Submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Electrical Engineering in the Graduate College of
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iii CACHE DESIGN AND PERFORMANCE IN A LARGE-SCALE SHARED-MEMORY MULTIPROCESSOR SYSTEM Yung-Chin Chen, Ph.D. Department of Electrical and Computer Engineering University of Illinois at Urbana-Champaign, 1993 Alexander V. Veidenbaum, Advisor The use of a private cache in each processor of large-scale
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Improving Memory Utilization in Cache Coherence Directories David J. Lilja Department of Electrical Engineering University of Minnesota 200 Union Street S.E. Minneapolis, MN 55455 (612) 625-5007 lilja@ee.umn.edu Pen-Chung Yew Center for Supercomputing Research and Development University of Illinois at
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The Impact of Parallel Loop Scheduling Strategies on Prefetching in a Shared-Memory Multiprocessor David J. Lilja Department of Electrical Engineering University of Minnesota 200 Union Street S.E. Minneapolis, MN 55455 Phone: (612) 625-5007 FAX: (612) 625-4583 E-mail: lilja@ee.umn.edu April 28, 1992
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Two Special Classes of Matrices Hsin-Chu Chen March 25, 1990
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ILL-CONDITIONING IN NEURAL NETWORK TRAINING PROBLEMS S. SAARINEN , R. BRAMLEY AND G. CYBENKO y
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COMPILER OPTIMIZATIONS FOR PARALLEL LOOPS WITH FINE-GRAINED SYNCHRONIZATION BY DING-KAI CHEN B.S., National Taiwan University, 1985 M.S., University of Illinois at Urbana Champaign, 1989 THESIS Submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Computer
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ASM Description with LIDEX Jos e Eduardo Moreira Wilson Vicente Ruggiero Departamento de Engenharia de Eletricidade, Escola Polit ecnica da Universidade de S~ao Paulo, Brasil Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign, USA February 1990 CSRD Report No.
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LIDEX Simulation Environment User's Manual Jos e Eduardo Moreira Wilson Vicente Ruggiero Departamento de Engenharia de Eletricidade, Escola Polit ecnica da Universidade de S~ao Paulo, Brasil Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign, USA February 1990
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LIDEX Reference Manual Jos e Eduardo Moreira Wilson Vicente Ruggiero Departamento de Engenharia de Eletricidade, Escola Polit ecnica da Universidade de S~ao Paulo, Brasil Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign, USA February 1990 CSRD Report No. 973
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Compiler-directed Data Prefetching in Multiprocessors with Memory Hierarchies Edward H. Gornish Elana D. Granston Alexander V. Veidenbaum Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign Urbana, Illinois, 61801
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PERFORMANCE OF THE FINITE STRIP METHOD FOR STRUCTURAL ANALYSIS ON A PARALLEL COMPUTER HSIN-CHU CHENy AND AI-FANG HEz
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BIT 30:268-288, 1990 A Parallel Method for Fast and Practical High-Order Newton Interpolation O. E gecio gluy, E. Gallopoulos and C. K. Ko cz May 1989 CSRD Report No. 921 y Department of Computer Science University of California Santa Barbara Santa Barbara, CA 93106. Center for Supercomputing Research
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LIDEX Tutorial Jos e Eduardo Moreira Wilson Vicente Ruggiero Departamento de Engenharia de Eletricidade, Escola Polit ecnica da Universidade de S~ao Paulo, Brasil Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign, USA February 1990 CSRD Report No. 972
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Run-Time Management of Lisp Parallelism and the Hierarchical Task Graph Program Representation Mario Furnari Istituto di Cib ernetica Via Toiano, 6 80072 - Arco Felice (Na) Italy Constan tine D. Polychronop oulos y Cen ter for Supercomputing Researc h and Developmen t Univ ersit y of Illinois 305 T alb
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SOLVING NAVIER{STOKES EQUATIONS ON THE CEDAR MULTI{CLUSTER SYSTEM JACQUES LAMINIEy AND ULRIKE MEIERz
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Analysis of a SIMD Computer Jos e Eduardo Moreira Wilson Vicente Ruggiero Departamento de Engenharia de Eletricidade, Escola Polit ecnica da Universidade de S~ao Paulo, Brasil Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign, USA February 1990 CSRD Report No.
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Autoscheduling in a Shared Memory Multiprocessor Jos e E. Moreira Constantine D. Polychronopoulos fmoreira,cdpg@csrd.uiuc.edu Center for Supercomputing Research and Development and Coordinated Science Laboratory University of Illinois at Urbana-Champaign 1308 W. Main St., Urbana, IL USA Presented at the
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Autoscheduling in a Distributed Shared-Memory Environment Jos e E. Moreira Constantine D. Polychronopoulos moreira@csrd.uiuc.edu cdp@csrd.uiuc.edu Center for Supercomputing Research and Development and Coordinated Science Laboratory University of Illinois at Urbana-Champaign 1308 W. Main St. Urbana, IL
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An Empirical Study of Fortran Programs for Parallelizing Compilers Zhiyu Shen i P Zhiyuan L en-Chung Yew I
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A Review of HDLs Jos e Eduardo Moreira Wilson Vicente Ruggiero Departamento de Engenharia de Eletricidade, Escola Polit ecnica da Universidade de S~ao Paulo, Brasil Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign, USA February 1990 CSRD Report No. 971
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On the Implementation and Effectiveness of Autoscheduling Jos e E. Moreira Constantine D. Polychronopoulos moreira@csrd.uiuc.edu, (217) 244-0049 cdp@csrd.uiuc.edu, (217) 244-4144 Fax: (217) 244-1351 Center for Supercomputing Research and Development and Coordinated Science Laboratory University of
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The LIDEX Approach Jos e Eduardo Moreira Wilson Vicente Ruggiero Departamento de Engenharia de Eletricidade, Escola Polit ecnica da Universidade de S~ao Paulo, Brasil Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign, USA February 1990 CSRD Report No. 970
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EXPERIMENTS WITH ELLIPTIC PROBLEM SOLVERS ON THE CEDAR MULTICLUSTER G. FRANK , E. GALLOPOULOS AND U. MEIERy
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Parallelization and Performance of Conjugate Gradient Algorithms on the Cedar hierarchical-memory Multiprocessor Ulrike Meier and Rudolf Eigenmann
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MaxPar: AN EXECUTION DRIVEN SIMULATOR FOR STUDYING PARALLEL SYSTEMS BY DING-KAI CHEN B.S., National Taiwan University, 1985 THESIS Submitted in partial fulfillment of the requirements for the degree of Master of Science in Computer Science in the Graduate College of the University of Illinois at
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The Impact of Synchronization and Granularity on Parallel Systems Ding-Kai Chen, Hong-Men Su, and Pen-Chung Yew Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign Urbana, Illinois, 61820
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Issues in the compile-time optimization of parallel programs S.P. Midkiff D.A. Padua
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CSRD report no. 952 Center for Supercomputing Research and Development hhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhh An Effective Synchronization Network for Hot-spot Accesses William Tsun-yuk Hsu and Pen-chung Yew June 8, 1992
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Volume Visualization Methods for Scientific Computing Peter Shirley Computer Science Department Indiana University Bloomington, IN. shirley@iuvax.cs.indiana.edu Allan Tuchman Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign Urbana, IL, 61801
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Matrix Visualization in the Design of Numerical Algorithms Allan M. Tuchman 1 Michael W. Berry 2 May 1989 1Center for Supercomputing Research and Development, University of Illinois at Urbana-Champaign, 305 Talbot Laboratory, 104 South Wright Street, Urbana, IL, 61801-2932. Research supported by the
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THE SIMULATION AND TUNING OF THE GLOBAL MEMORY SUBSYSTEM OF A MULTIPROCESSOR BY THOMAS MARTIN CONTE B.E.E., University of Delaware, 1986 THESIS Submitted in partial fulfillment of the requirements for the degree of Master of Science in Electrical Engineering in the Graduate College of the University of
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The PERFECT Club Benchmarks: Effective Performance Evaluation of Supercomputers The PERFECT1 Club: M. Berry, D. Chen, P. Koss, D. Kuck, S. Lo, Y. Pang, L. Pointer, R. Roloff, A. Sameh2, E. Clementi, S. Chin, D. Schneider3 9, G. Fox, P. Messina, D. Walker4, C. Hsiung, J. Schwarzmeier5 9, K. Lue, S.
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Event Synchronization Analysis for Debugging Parallel Programs Perry A. Emrath Sanjoy Ghosh David A. Padua Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign 305 Talbot Laboratory 104 South Wright Street Urbana, Illinois 61801
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ALGORITHMIC DESIGN ON THE CEDAR MULTIPROCESSOR Michael Berry Hsin-Chu Chen Efstratios Gallopoulos Ulrike Meier Allan Tuchman Harry Wijshoff Gung-Chung Yang April 1, 1989
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Cedar Synchronization Processor Instruction Set Reference David Pointer Greg Jaxon Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign Urbana, Illinois 61801 July 1990 hhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhh This work was supported in part by the U.S. Department of
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PRECONDITIONED ITERATIVE SOLVERS BASED ON RANK-ONE UPDATES FOR NONSYMMETRIC LINEAR SYSTEMS Ulrike Meier Yang, Kyle A. Gallivan CSL, University of Illinois 1308 W. Main St. Urbana, IL 61801, USA e-mail: meier@csrd.uiuc.edu, gallivan@csrd.uiuc.edu July 19, 1994 1 Introduction There still is a great need
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Preconditioned Conjugate Gradient-Like Methods for Nonsymmetric Linear Systems 1 Ulrike Meier Yang 2 July 19, 1994 1 This research was supported by the U.S. Department of Energy under Grant No. DE-FG02- 85ER25001. 2 Center for Supercomputing Research and Development, University of Illinois at
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CSRD report number 1280. Condensed version to appear in Proceedings of Supercomputing 1993 . Execution-Driven Tools for Parallel Simulation of Parallel Architectures and Applications (*) David K. Poulsen and Pen-Chung Yew Center for Supercomputing Research and Development University of Illinois
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In Proc. DAGS'94 Symposium on Parallel Computing and Problem Solving Environments F. Makedon ed. pp 11{25, Dartmouth College, July 1994 An environment for the rapid prototyping and development of numerical programs and li- braries for scientific computation L. DeRose, K. Gallivan, E. Gallopoulos, B.
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Submitted to ICPP '94 Statement Re-ordering for DOACROSS Loops Ding-Kai Chen Pen-Chung Yew fdkchen,yewg@csrd.uiuc.edu Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign Urbana, Illinois, 61820 January 17, 1994
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1. Introduction In this paper we present an overviewoftwo fundamental approaches for solving dense symmetric eigensystems on a multiprocessor.The rst approach, discussed in Section 2, is based upon Jacobi diagonalization methods which offer good parallelism for machines such as the Alliant FX/8. Tw
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The Range Test: A Dependence Test for Symbolic, Non-linear Expressions William Blume Rudolf Eigenmann blume@csrd.uiuc.edu eigenman@csrd.uiuc.edu Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign 1308 W. Main St., Urbana, Illinois 61801-2307
open this document and view contentsftp://sp2.csrd.uiuc.edu/pub/CSRD_Reports/reports/1338.ps.gz, 19940812
Restructuring Fortran Programs for Cedar Rudolf Eigenmann, Jay Hoeflinger, Greg Jaxon, Zhiyuan Li, David Padua Center for Supercomputing Research & Development University of Illinois at Urbana-Champaign Urbana, Illinois 61801
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Polaris: The Next Generation in Parallelizing Compilers Bill Blume Rudolf Eigenmann Keith Faigin John Grout Jay Hoeflinger David Padua Paul Petersen Bill Pottenger Lawrence Rauchwerger Peng Tu Stephen Weatherford
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1 1 MEMORY LATENCY REDUCTION VIA DATA PREFETCHING AND DATA FORWARDING IN SHARED MEMORY MULTIPROCESSORS BY DAVID KRISTIAN POULSEN B.S., University of Wisconsin-Madison, 1984 M.S., Syracuse University, 1988 THESIS Submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy
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Gated SSA Based Demand-Driven Symbolic Analysis Peng Tu and David Padua Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign 1308 W. Main Street, Urbana, Illinois 61801-2307 tu,padua@csrd.uiuc.edu 1 Introduction It has become increasingly evident that symbolic
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AN OVERVIEW OF SYMBOLIC ANALYSIS TECHNIQUES NEEDED FOR THE EFFECTIVE PARALLELIZATION OF THE PERFECT BENCHMARKS R William Blume and Rudolf Eigenmann Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign blume@csrd.uiuc.edu and eigenman@csrd.uiuc.edu
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Parallel Performance of a Combustion Chemistry Simulation Gregg Skinner Rudolf Eigenmann Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign September 1, 1994
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Symbolic Range Propagation William Blume Rudolf Eigenmann blume@csrd.uiuc.edu eigenman@csrd.uiuc.edu Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign 1308 W. Main St., Urbana, Illinois 61801-2307 September 20, 1994
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The Privatizing DOALL Test: A Run-Time Technique for DOALL Loop Identification and Array Privatization Lawrence Rauchwerger and David Padua Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign 1308 W. Main St., Urbana, IL 61801
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Parallelizing WHILE Loops for Multiprocessor Systemsy Lawrence Rauchwerger and David Padua Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign 1308 W. Main St., Urbana, IL 61801 Corresponding Author: Lawrence Rauchwerger. email: rwerger@csrd.uiuc.edu telephone:
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Speculative Run-Time Parallelization of Loopsy Lawrence Rauchwerger and David Padua Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign 1308 W. Main St., Urbana, IL 61801 Corresponding Author: Lawrence Rauchwerger. email: rwerger@csrd.uiuc.edu telephone: (217)
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Parallelizing WHILE Loops for Multiprocessor Systemsy Lawrence Rauchwerger and David Padua Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign 1308 W. Main St., Urbana, IL 61801 Corresponding Author: Lawrence Rauchwerger. email: rwerger@csrd.uiuc.edu telephone:
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The Privatizing DOALL Test: A Run{Time Technique for DOALL Loop Identification and Array Privatizationyz Lawrence Rauchwerger and David Padua Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign 1308 W. Main St., Urbana, IL 61801
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Speculative Run-Time Parallelization of Loopsy Lawrence Rauchwerger and David Padua Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign 1308 W. Main St., Urbana, IL 61801 Corresponding Author: Lawrence Rauchwerger. email: rwerger@csrd.uiuc.edu telephone: (217)
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The Privatizing DOALL Test: A Run-Time Technique for DOALL Loop Identification and Array Privatization Lawrence Rauchwerger and David Padua Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign 1308 W. Main St., Urbana, IL 61801
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The Privatizing DOALL Test: A Run{Time Technique for DOALL Loop Identification and Array Privatizationyz Lawrence Rauchwerger and David Padua Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign 1308 W. Main St., Urbana, IL 61801
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The parallel solution of nonsymmetric sparse linear systems using the H* reordering and an associated factorization. K. A. Gallivan B. A. Marsolf Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign Urbana, Illinois 61801 H. A. G. Wijshoffy High Performance
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ADAPTIVE AND INTEGRATED DATA CACHE PREFETCHING FOR SHARED-MEMORY MULTIPROCESSORS BY EDWARD H. GORNISH B.S., Massachusetts Institute of Technology, 1986 M.S., University of Illinois, 1989 THESIS Submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Computer
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AUTOMATIC PARALLELIZATION OF PROLOG PROGRAMS BY DAVID CHRISTOPHER SEHR B.S., Butler University, 1985 M.S., University of Illinois, 1988 THESIS Submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Computer Science in the Graduate College of the University of
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The LRPD Test: Speculative Run Time Parallelization of Loops with Privatization and Reduction Parallelization y Lawrence Rauchwerger and David Padua Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign 1308 W. Main St., Urbana, IL 61801 Corresponding Author:
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In Proc. of the IEEE/USP International Workshop on High Performance Computing; Compiler and Tools for Parallel Processing. J. Zuffo ed. pp 97 112, University of S ao Paulo, SP Brazil, March 1994 An Inference Mechanism for the Compilation of Interactive Array Languages Luiz De Rose and David Padua March
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Efficient Building and Placing of Gating Functions Peng Tu and David Padua Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign 1308 W. Main Street, Urbana, Illinois 61801-2307 tu,padua@csrd.uiuc.edu (217) 333-6884 1 Introduction The Gated Single-Assignment (GSA)
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Perfect: Performance Evaluation for Cost-Effective Transformations Report 2 Robert Pirsig, Editor 1 May 21, 1993 1Editor's present address: Center for Supercomputing Research and Development, University of Illinois, Urbana, IL 61801. This work was supported by the National Science Foundation under Grant
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A Year's Profile of Academic Supercomputer Users Using the CRAY Hardware Performance Monitor Hui Gao 1 Center for Supercomputing Research and Development 465 CSRL, 1308 W. Main St. Urbana, IL 61801 John L. Larson 2 Center for Supercomputing Research and Development 465 CSRL, 1308 W. Main St. Urbana, IL
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Privatization and Distribution of Arrays A Preliminary Proposal Peng Tu
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THE SYNERGETIC EFFECT OF COMPILER, ARCHITECTURE, AND MANUAL OPTIMIZATIONS ON THE PERFORMANCE OF CFD ON MULTIPROCESSORS Masayuki Kuba , Constantine D. Polychronopoulos, Kyle Gallivan Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign, IL 61801 Email: fkuba, cdp,
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On the Paralleliztion of a CFD code Masayuki Kuba March 27, 1995 1 Contents 1 Introduction 4 2 Goals of This Research 5 2.1 Goals and Methodology : : : : : : : : : : : : : : : : : : : : : 5 2.2 Related Work : : : : : : : : : : : : : : : : : : : : : : : : : : : 6 3 General Description of a CFD
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EXPLOITING PARALLELISM IN SETL PROGRAMS BY JOHN MICHAEL JOZWIAK B.S., University of Illinois, 1988 THESIS Submitted in partial fulfillment of the requirements for the degree of Master of Science in Computer Science in the Graduate College of the University of Illinois at Urbana-Champaign, 1993 Urbana,
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Parallelization in the Presence of Generalized Induction and Reduction Variables Bill Pottenger and Rudolf Eigenmann Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign
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A Compiler-Directed Cache Coherence Scheme with Improved Intertask Locality Lynn Choi Pen-Chung Yew Center for Supercomputing R & D Department of Computer Science University of Illinois University of Minnesota Urbana, IL 61801-1351 Minneapolis, MN 55455-0519
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Interprocedural Array Data-Flow Analysis for Cache Coherence Lynn Choi y Pen-Chung Yew Center for Supercomputing R & D Department of Computer Science University of Illinois University of Minnesota Urbana, IL 61801-1351 Minneapolis, MN 55455-0519 lchoi@csrd.uiuc.edu yew@cs.umn.edu (217)333-0969
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EFFICIENT SCHEDULING OF PARALLEL TASKS IN A MULTIPROGRAMMING ENVIRONMENT BY DALE ALLAN SCHOUTEN B.S.C.E., University of Arizona, 1986 M.S., University of Illinois, 1990 THESIS Submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Computer Science in the Graduate
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A Rational Lanczos Algorithm for Model Reduction K. Gallivan and E. Grimme Coordinated Science Laboratory University of Illinois at Urbana-Champaign Urbana IL 61801, USA P. Van Dooren Center for Systems Engineering and Applied Mechanics Universit e Catholique de Louvain B-1348 Louvain-la-Neuve, BELGIUM
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PAD E APPROXIMATION OF LARGE-SCALE DYNAMIC SYSTEMS WITH LANCZOS METHODS K. Gallivan, E. Grimme and P. Van Dooren Coordinated Science Laboratory University of Illinois at Urbana-Champaign 1308 West Main Street Urbana, IL 61801
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On some modifications of the Lanczos algorithm and the relation with Pad e approximations K. Gallivan, E. Grimme, D. Sorensen and P. Van Dooren
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SOLVING LARGE NONSYMMETRIC SPARSE LINEAR SYSTEMS USING MCSPARSE K. A. GALLIVAN , B. A. MARSOLF AND H. A. G. WIJSHOFFy
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On Solving Block Toeplitz Systems Using a Block Schur Algorithm Srikanth Thirumalai, Kyle Gallivan and Paul Van Dooren April 10, 1995
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Appl. Math. Lett. Vol. 7, No. 5, pp. 75{80, 1994 Pergamon Copyright c 1994 Elsevier Science Ltd Printed in Great Britain. All rights reserved 0893-9659/94 $7:00 + :00 Asymptotic Waveform Evaluation via a Lanczos Method K. Gallivan, E. Grimme and P. Van Dooren Coordinated Science Laboratory, University
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1 A BLOCK TOEPLITZ LOOK-AHEAD SCHUR ALGORITHM KYLE GALLIVAN Coordinated Science Laboratory University of Illinois Urbana, IL USA gallivan@csrd.uiuc.edu SRIKANTH THIRUMALAI Coordinated Science Laboratory University of Illinois Urbana, IL USA srikanth@csrd.uiuc.edu PAUL VAN DOOREN Cesame Universit e
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QR factorization of rank deficient block Toeplitz matrices Kyle Gallivan, Srikanth Thirumalai and Paul Van Dooren University of Illinois at Urbana Champaign Coordinated Science Laboratory 1308 W Main, Urbana, IL 61801 The Schur algorithm can be generalized to obtain the QR factorization of block
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High Performance Algorithms for Toeplitz and block Toeplitz matrices K. A. Gallivan S. Thirumalai Coordinated Science Laboratory, University of Illinois at Urbana-Champaign, Urbana IL, USA P. Van Dooren V. Vermaut Universit e Catholique de Louvain, Louvain, Belgium 1 Introduction Algorithms to solve
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A look-ahead Schur Algorithm Kyle Gallivan Srikanth Thirumalai Paul Van Dooren
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INLINE EXPANSION FOR THE POLARIS RESEARCH COMPILER BY JOHN ROBERT GROUT B.S., Worcester Polytechnic Institute, 1981 THESIS Submitted in partial fulfillment of the requirements for the degree of Master of Science in Computer Science in the Graduate College of the University of Illinois at
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To appear in a forthcoming volume of The NATO ISO Series on Parallel Numerical Algorithms. On the Development of Libraries and their use in Applications Kyle A. Gallivan, Bret A. Marsolf, William Jalby, and Ahmed H. Sameh May 1995 CSRD Report No. 1341 Center for Supercomputing Research and Development
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AUTOMATIC ARRAY PRIVATIZATION AND DEMAND-DRIVEN SYMBOLIC ANALYSIS BY PENG TU B.S.Eng., Shanghai Jiao Tong University, 1984 M.S.Eng., Shanghai Jiao Tong University, 1987 THESIS Submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Computer Science in the Graduate
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c Copyright by William Joseph Blume 1995 SYMBOLIC ANALYSIS TECHNIQUES FOR EFFECTIVE AUTOMATIC PARALLELIZATION BY WILLIAM JOSEPH BLUME M.S., University of Illinois, 1992 B.S., University of Illinois, 1989 THESIS Submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy
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1 A Uniform Internal Representation for High-Level and Instruction-Level Transformations Eduard Ayguad , Cristina Barrado, Jes s Labarta, David L pez, Susana Moreno, David Padua, and Mateo Valero Departament d Arquitectura de Computadors Universitat Polit cnica de Catalunya Barcelona 1 Introduction
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A STUDY ON INSTRUCTION-LEVEL PARALLELISM ARCHITECTURES AND OVERHEAD ANALYSIS OF PARALLEL EXECUTION BY ADAM STUART BLOCK B.S., University of Illinois at Urbana-Champaign, 1994 THESIS Submitted in partial fulfillment of the requirements for the degree of Master of Science in Electrical Engineering in the
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INTERCONNECTION NETWORKS AND DATA PREFETCHING FOR LARGE-SCALE MULTIPROCESSORS: DESIGN AND PERFORMANCE BY SUNIL KIM B.S., Seoul National University, 1985 M.S., Seoul National University, 1987 THESIS Submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Computer
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Idiom Recognition in the Polaris Parallelizing Compiler Bill Pottenger and Rudolf Eigenmann potteng@csrd.uiuc.edu, eigenman@csrd.uiuc.edu Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign 1308 West Main Street, Urbana, Illinois 61801-2307
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Effective Automatic Parallelization with Polaris William Blume, Rudolf Eigenmann, Keith Faigin, John Grout, Jay Hoeflinger, David Padua, Paul Petersen, William Pottenger, Lawrence Rauchwerger, Peng Tu and Stephen Weatherford Center for Supercomputing Research and Development Coordinated Science
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c Copyright by Stephen Wilson Turner, 1995 PERFORMANCE ANALYSIS OF MULTIPROCESSOR INTERCONNECTION NETWORKS USING A BURST-TRAFFIC MODEL BY STEPHEN WILSON TURNER B.S.E.E., Ohio State University, 1986 M.S., University of Illinois, 1989 THESIS Submitted in partial fulfillment of the requirements for the
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Gated SSA-Based Demand-Driven Symbolic Analysis for Parallelizing Compilers Peng Tu and David Padua Center for Supercomputing Research and Development Coordinated Science Laboratory, University of Illinois at Urbana-Champaign 1308 W. Main Street, Urbana, Illinois 61801-2307 tu,padua@csrd.uiuc.edu
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INDUCTION VARIABLE SUBSTITUTION AND REDUCTION RECOGNITION IN THE POLARIS PARALLELIZING COMPILER BY WILLIAM MORTON POTTENGER B.S., University of Alaska, Fairbanks, 1989 B.A., Lehigh University, 1980 THESIS Submitted in partial fulfillment of the requirements for the degree of Master of Science in
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Polaris: Improving the Effectiveness of Parallelizing Compilers William Blume, Rudolf Eigenmann, Keith Faigin, John Grout, Jay Hoeflinger, David Padua, Paul Petersen, William Pottenger, Lawrence Rauchwerger, Peng Tu and Stephen Weatherford Center for Supercomputing Research and Development Coordinated
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A Scalable Method for Run Time Loop Parallelization Lawrence Rauchwergeryx Nancy M. Amatoz David A. Paduax Center for Supercomputing R&D Department of Computer Science Center for Supercomputing R&D University of Illinois Texas A&M University University of Illinois rwerger@csrd.uiuc.edu amato@cs.tamu.edu
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Run Time Methods for Parallelizing Partially Parallel Loopsx Lawrence Rauchwergery Nancy M. Amatoz David A. Paduay University of Illinois Texas A&M University University of Illinois
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THE POLARIS INTERNAL REPRESENTATION BY KEITH AARON FAIGIN B.A., Williams College, 1992 THESIS Submitted in partial fulfillment of the requirements for the degree of Master of Science in Computer Science in the Graduate College of the University of Illinois at Urbana-Champaign, 1994 Urbana, Illinois iii
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The Performance Impact of Granularity Control and Functional Parallelism Jos e E. Moreiray Dale Schoutenz Constantine Polychronopoulosz moreira@watson.ibm.com fschouten,cdpg@csrd.uiuc.edu y IBM T. J. Watson Research Center Yorktown Heights, NY 10598-0218 z Center for Supercomputing Research and
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Demand-driven, Symbolic Range Propagation William Blume Rudolf Eigenmann Hewlett Packard, Cupertino, California Purdue University, West Lafayette, Indiana
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Run-Time Parallelization: A Framework for Parallel Computation Lawrence Rauchwerger, Ph.D. Department of Computer Science University of Illinois at Urbana-Champaign, 1995 David Padua, Advisor The goal of parallelizing, or restructuring, compilers is to detect and exploit parallelism in sequential
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c Copyright by Lawrence Rauchwerger 1995 RUN-TIME PARALLELIZATION: A FRAMEWORK FOR PARALLEL COMPUTATION BY LAWRENCE RAUCHWERGER Dipl., Institutul Politehnic Bucure sti, 1980 M.S., Stanford University, 1987 THESIS Submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy
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The Generation of Optimized Codes using Nonzero Structure Analysis Kyle A. Gallivan, Bret A. Marsolf, Aart J. C. Bik, and Harry A. G. Wijshoff September 1995 CSRD Report No. 1451 Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign 1308 West Main Street Urbana,
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In the preliminary proceedings of the 8th International Workshop on Languages and Compilers for Parallel Computing. pp 18.1-18.18, Columbus, Ohio, August 1995 A MATLAB Compiler and Restructurer for the Development of Scientific Libraries and Applications L. DeRose, K. Gallivan, E. Gallopoulos, B.
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Eliminating Stale Data References through Array Data-Flow Analysis Lynn Choi Pen-Chung Yew Center for Supercomputing R & D Department of Computer Science University of Illinois University of Minnesota Urbana, IL 61801-1351 Minneapolis, MN 55455-0519 lchoi@csrd.uiuc.edu yew@cs.umn.edu (217)333-0969
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Compiler and Hardware Support for Cache Coherence in Large-Scale Multiprocessors: Design Considerations and Performance Evaluation Lynn Choi Pen-Chung Yew Center for Supercomputing R & D Department of Computer Science University of Illinois University of Minnesota Urbana, IL 61801-1351 Minneapolis, MN
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A FAMILY OF PRECONDITIONED ITERATIVE SOLVERS FOR SPARSE LINEAR SYSTEMS BY ULRIKE MEIER YANG Dipl., Ruhruniversit at Bochum, 1983 THESIS Submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Computer Science in the Graduate College of the University of Illinois at
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A NEW FAMILY OF PRECONDITIONED ITERATIVE SOLVERS FOR NONSYMMETRIC LINEAR SYSTEMS Ulrike Meier Yang and Kyle A. Gallivan Coordinated Science Laboratory University of Illinois 1308 W. Main St. Urbana, IL 61801, USA e-mail: meier@csrd.uiuc.edu, gallivan@csrd.uiuc.edu
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Practical Parallelization of Molecular Dynamics on Shared and Distributed Memory Machines Masayuki Kuba , Marie-Christine Brunet, Constantine D. Polychronopoulos Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign, IL 61801 Email: fkuba, maiki,
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In OON-SKI'94 Proceedings of the Second Annual Object-Oriented Numerics Conference pp 93{106, Sunriver, Oregon, April 1994 Practical Issues Related to Developing Object- Oriented Numerical Libraries K. Gallivan and B. Marsolf April 1994 CSRD Report No. 1340 Center for Supercomputing Research and
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To appear in the Proceedings of KBUP'95 - First International Workshop on Knowledge-Based System for the (re)Use of Program Libraries. Sophia Antipolis - France, November 1995 FALCON: An Environment for the Development of Scientific Libraries and Applications L. De Rosey, K. Gallivany, E. Gallopoulosy;
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Slides presented at the 1995 MATLAB Conference. Cambridge, MA, October 1995 An Environment for Interactive Development of Software Using MATLAB L. De Rosey, K. Gallivany, E. Gallopoulosy; , B. Marsolfy, and D. Paduay October 1995 CSRD Report No. 1453 y Center for Supercomputing Research and Development
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ON THE IMPLEMENTATION AND EFFECTIVENESS OF AUTOSCHEDULING FOR SHARED-MEMORY MULTIPROCESSORS BY JOS E EDUARDO MOREIRA Bach., Physics, Universidade de S~ao Paulo, 1987 Engr., Electrical Engineering, Universidade de S~ao Paulo, 1988 Mestr., Electrical Engineering, Universidade de S~ao Paulo, 1990 THESIS
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A data prefetch mechanism for accelerating general-purpose computation Luddy Harrison (harrison@csrd.uiuc.edu) UI Dept. of Computer Science and Connected Components Corporation Sharad Mehrotra (mehrotra@csrd.uiuc.edu) CSRD and UI Dept. of Computer Science 8 May 1994 (Last revised 9 March 1995) 1
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Optimizing Instruction Cache Performance for Operating System Intensive Workloads1 Josep Torrellas, Chun Xia, and Russell Daigle2 Center for Supercomputing Research and Development and Computer Science Department University of Illinois at Urbana-Champaign, IL 61801
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Comparing the Performance and Programmability of the DASH and Cedar Multiprocessors for Scientific Loads Josep Torrellas and David Koufaty Center for Supercomputing Research and Development and Computer Science Department University of Illinois at Urbana-Champaign, IL 61801 Email:
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An Efficient Algorithm for the Run-Time Parallelization of Doacross Loops1 Ding-Kai Chen2, David A. Oesterreich3, Josep Torrellas, and Pen-Chung Yew4 Center for Supercomputing Research and Development and Computer Science Department University of Illinois at Urbana-Champaign, IL 61801
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Report of a Workshop on Research Directions in Integrating Numerical Analysis, Symbolic Computing, Computational Geometry, and Artificial Intelligence for Computational Science held in Washington, D.C., on April 11 12, 1991. Future Research Directions in Problem Solving Environments for Computational
open this document and view contentsftp://sp2.csrd.uiuc.edu/pub/CSRD_Reports/reports/1378.ps.gz, 19951218
To appear in J. Comput. Appl. Math., 66, 1996. A hybrid block GMRES method for nonsymmetric systems with multiple right-hand sides V. Simonciniy and E. Gallopoulos September 1994 September 1995 revision CSRD Report No. 1378 y IMGA-CNR Modena, Italy Center for Supercomputing Research and Development
open this document and view contentsftp://sp2.csrd.uiuc.edu/pub/CSRD_Reports/reports/1319.ps.gz, 19951218
J. Comput. Appl. Math., 59:349 380, 1995. Incomplete Partial Fractions for Parallel Evaluation of Rational Matrix Functions D. Calvetti , E. Gallopoulosy and L. Reichelz November 1993 CSRD Report No. 1319 March 1994 revision Stevens Institute of Technology Department of Pure and Applied Mathematics
open this document and view contentsftp://sp2.csrd.uiuc.edu/pub/CSRD_Reports/reports/1467.ps.gz, 19951218
Improving the Data Cache Performance of Multiprocessor Operating Systems1 Chun Xia and Josep Torrellas Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign, IL 61801 xia,torrella@csrd.uiuc.edu
open this document and view contentsftp://sp2.csrd.uiuc.edu/pub/CSRD_Reports/reports/1470.ps.gz, 19951218
To appear in Linear Algebra and its Applications Convergence Properties of Block GMRES and Matrix Polynomials V. Simonciniy and E. Gallopoulos April 1994 11/94 (rev.) CSRD Report No. 1470 yDipartimento di Fisica Universit a degli Studi di Bologna Bologna, Italy EU Center for Supercomputing Research and
open this document and view contentsftp://sp2.csrd.uiuc.edu/pub/CSRD_Reports/reports/1465.ps.gz, 19951218
Scalable Shared-Memory Architectures Introduction to the Minitrack Josep Torrellas Center for Supercomputing Research and Development and Computer Science Department University of Illinois at Urbana-Champaign, IL 61801, USA 1 Background Shared-memory multiprocessing is emerging as a popular approach to
open this document and view contentsftp://sp2.csrd.uiuc.edu/pub/CSRD_Reports/reports/1468.ps.gz, 19951218
Distance-Adaptive Update Protocols for Scalable Shared-Memory Multiprocessors1 Alain Raynaud, Zheng Zhang, and Josep Torrellas Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign, IL 61801 raynaud,zzhang,torrella@csrd.uiuc.edu
open this document and view contentsftp://sp2.csrd.uiuc.edu/pub/CSRD_Reports/reports/1242.ps.gz, 19951218
SIAM J. Sci. Comput., 16(4):917{933, July 1995 (Replaces CSRD Report 1242.) An Iterative Method for Nonsymmetric Systems with Multiple Right-Hand Sides V. Simonciniy and E. Gallopoulos y IMGA-CNR Modena, Italy Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign
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Speeding up Irregular Applications in Shared-Memory Multiprocessors: Memory Binding and Group Prefetching1 Zheng Zhang and Josep Torrellas Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign, IL 61801 Email: zzhang,torrella@csrd.uiuc.edu
open this document and view contentsftp://sp2.csrd.uiuc.edu/pub/CSRD_Reports/reports/1464.ps.gz, 19951218
Data Forwarding in Scalable Shared-Memory Multiprocessors1 D. A. Koufaty, X. Chen, D. K. Poulsen2, and J. Torrellas Center for Supercomputing Research and Development and Computer Science Department University of Illinois at Urbana-Champaign, IL 61801 koufaty,xchen,poulsen,torrella@csrd.uiuc.edu
open this document and view contentsftp://sp2.csrd.uiuc.edu/pub/CSRD_Reports/reports/1386.ps.gz, 19951219
The Performance of the Cedar Multistage Switching Network1 Josep Torrellas and Zheng Zhang Center for Supercomputing Research and Development and Computer Science Department University of Illinois at Urbana-Champaign, IL 61801
open this document and view contentsftp://sp2.csrd.uiuc.edu/pub/CSRD_Reports/reports/1469.ps.gz, 19951219
Low Perturbation Address Trace Collection for Operating System, Multiprogrammed, and Parallel Workloads in Multiprocessors1 Russell Daigle2, Chun Xia, and Josep Torrellas Center for Supercomputing Research and Development and Computer Science Department University of Illinois at Urbana-Champaign, IL
open this document and view contentsftp://sp2.csrd.uiuc.edu/pub/CSRD_Reports/reports/1181.ps.gz, 19960109
PARALLEL OCEAN CIRCULATION MODELING ON CEDAR BY LUIZ ANT^ONIO DE ROSE Bach., Universidade de Bras lia, 1978 M.Stat., Universidade de Bras lia, 1982 THESIS Submitted in partial fulfillment of the requirements for the degree of Master of Science in Computer Science in the Graduate College of the
open this document and view contentsftp://sp2.csrd.uiuc.edu/pub/CSRD_Reports/reports/1471.ps.gz, 19960201
Slides presented at the Computer Systems Seminar, at the University of Illinois at UrbanaChampaign. January 1996 Accelerating MATLAB Programs with FALCON Luiz De Rose and David Padua January 1996 CSRD Report No. 1471 Center for Supercomputing Research and Development University of Illinois at
open this document and view contentsftp://sp2.csrd.uiuc.edu/pub/CSRD_Reports/reports/1476.ps.gz, 19960221
Investigation of the Page Fault Performance of Cedar Bret Marsolf February 1996 CSRD Report No. 1476 Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign 1308 West Main Street Urbana, Illinois 61801 Investigation of the Page Fault Performance of Cedar Bret
open this document and view contentsftp://sp2.csrd.uiuc.edu/pub/CSRD_Reports/reports/1448.ps.gz, 19960222
In C.-H. Huang, P.Sadayappan, U. Banerjee, D. Gelernter, A. Nicolau, and D. Padua (Editors), Languages and Compilers for Parallel Computing, pages 269-288. Springer-Verlag, August 1995. (8th International Workshop, LCPC'95, Columbus OH.) FALCON: A MATLAB Interactive Restructuring Compiler L. DeRose, K.
open this document and view contentsftp://sp2.csrd.uiuc.edu/pub/CSRD_Reports/reports/1180.ps.gz, 19960229
mdb - Xylem Parallel Debugger User's Guide Perry Emrath Bret Marsolf Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign 305 Talbot Laboratory 104 South Wright St. Urbana, Illinois 61801-2932 March 31, 1995
open this document and view contentsftp://sp2.csrd.uiuc.edu/pub/CSRD_Reports/reports/1142.ps.gz, 19960229
MCSPARSE: A Parallel Sparse Unsymmetric Linear System Solver K. A. Gallivan, B. A. Marsolf, and H. A. G. Wijshoff August 1991 CSRD Report No. 1142 Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign 1308 West Main Street Urbana, Illinois 61801 MCSPARSE: A
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To appear in Journal of Parallel and Distributed Computing The Design and Performance Evaluation of the DI-multicomputer Lynn Choi Andrew A. Chien Center for Supercomputing R & D Department of Computer Science University of Illinois University of Illinois Urbana, IL 61801-1351 Urbana, IL 61801
open this document and view contentsftp://sp2.csrd.uiuc.edu/pub/CSRD_Reports/reports/1477.ps.gz, 19960304
Appears in the proceedings of the 8th IEEE International Parallel Processing Symposium '94 Integrating Networks and Memory Hierarchies in a Multicomputer Node Architecture Lynn Choi Andrew A. Chien CSRD Department of Computer Science University of Illinois University of Illinois Urbana, IL 61801 Urbana,
open this document and view contentsftp://sp2.csrd.uiuc.edu/pub/CSRD_Reports/reports/1479.ps.gz, 19960313
c Copyright by Chun Xia 1996 EXPLOITING MULTIPROCESSOR MEMORY HIERARCHIES FOR OPERATING SYSTEMS BY CHUN XIA B.Engr., Tsinghua University, 1985 M.Engr., Tsinghua University, 1989 THESIS Submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Computer Science in the
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To appear in the Proceedings of the 10th ACM International Conference on Supercomputing - ICS'96. Philadelphia, PA, May 1996 A MATLAB to Fortran 90 Translator and its Effectiveness Luiz De Rose and David Padua March 1996 CSRD Report No. 1462 Center for Supercomputing Research and Development University
open this document and view contentsftp://sp2.csrd.uiuc.edu/pub/CSRD_Reports/reports/1481.ps.gz, 19960322
Appears in Lecture Notes in Computer Science, LCPC '95 Interprocedural Array Data-Flow Analysis for Cache Coherence Lynn Choi1 and Pen-Chung Yew2 1 Center for Supercomputing Research and Development, University of Illinois, Urbana, IL 61801-1351, USA 2 Department of Computer Science, University of
open this document and view contentsftp://sp2.csrd.uiuc.edu/pub/CSRD_Reports/reports/1482.ps.gz, 19960322
To appear in the 23rd ACM Annual International Symposium on Computer Architecture '96 Compiler and Hardware Support for Cache Coherence in Large-Scale Multiprocessors: Design Considerations and Performance Study Lynn Choi University of Illinois at Urbana-Champaign Center for Supercomputing R & D Urbana,
open this document and view contentsftp://sp2.csrd.uiuc.edu/pub/CSRD_Reports/reports/1456.ps.gz, 19960322
Targeting a Shared-Address-Space Version of the Seismic Benchmark Seis1.1 Bill Pottenger and Rudolf Eigenmann Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign 1308 West Main Street, Urbana, Illinois 61801-2307 217-333-6578, fax: 217-244-1351
open this document and view contentsftp://sp2.csrd.uiuc.edu/pub/CSRD_Reports/reports/1480.ps.gz, 19960322
Eliminating Stale Data References through Array Data-Flow Analysis Lynn Choi University of Illinois at Urbana-Champaign Center for Supercomputing R & D 1308 West Main Street Urbana, IL 61801-1351 lchoi@csrd.uiuc.edu Pen-Chung Yew University of Minnesota Department of Computer Science 200 Union Street,
open this document and view contentsftp://sp2.csrd.uiuc.edu/pub/CSRD_Reports/reports/1484.ps.gz, 19960326
HARDWARE AND COMPILER SUPPORT FOR CACHE COHERENCE IN LARGE-SCALE SHARED-MEMORY MULTIPROCESSORS BY LYNN CHOI B.S., Seoul National University, 1986 M.S., Seoul National University, 1988 THESIS Submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Computer Science
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Advanced Program Restructuring for High-Performance Computers with Polaris William Blume Ramon Doallo Rudolf Eigenmann John Grout Jay Hoeflinger Thomas Lawrence Jaejin Lee David Padua Yunheung Paek Bill Pottenger Lawrence Rauchwerger Peng Tu Center for Supercomputing Research and Development, University
open this document and view contentsftp://sp2.csrd.uiuc.edu/pub/CSRD_Reports/reports/1483.ps.gz, 19960429
To Appear in the 1996 International Conference on Parallel Processing PROGRAM ANALYSIS FOR CACHE COHERENCE: BEYOND PROCEDURAL BOUNDARIES Lynn Choi Pen-Chung Yew Microprocessor Group Department of Computer Science Intel Corporation University of Minnesota Santa Clara, CA 95052 Minneapolis, MN 55455
open this document and view contentsftp://sp2.csrd.uiuc.edu/pub/CSRD_Reports/reports/1489.ps.gz, 19960506
Outline of a Roadmap for Compiler Technology May 2, 1996 3 New compiler algorithms are needed for explicitly parallel programming languages. Some of these algorithms are necessary to deal with resource allocation and overhead. Others are necessary to allow the application of traditional optimizations to
open this document and view contentsftp://sp2.csrd.uiuc.edu/pub/CSRD_Reports/reports/1490.ps.gz, 19960507
Non-Linear and Symbolic Data Dependence Testing William Blume Rudolf Eigenmann Hewlett-Packard, California Purdue University, Indiana bblume@hpclopt.cup.hp.com eigenman@ecn.purdue.edu April 19, 1996
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Multiprocessor Cache Coherence : The Compiler-Directed Approach Lynn Choi Microprocessor Group Intel Corporation 2200 Mission College Blvd Santa Clara, CA 95052 Email : lchoi@mipos2.intel.com Hock-Beng Lim Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign 443
open this document and view contentsftp://sp2.csrd.uiuc.edu/pub/CSRD_Reports/reports/1494.ps.gz, 19960625
oe-SSA and its Construction through Symbolic Interpretation Hideki Saito Constantine D. Polychronopoulos Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign 1308 W. Main St., Urbana, IL 61801 U.S.A. fsaito, cdpg@csrd.uiuc.edu May 30, 1996
open this document and view contentsftp://sp2.csrd.uiuc.edu/pub/CSRD_Reports/reports/1392.ps.gz, 19960820
On the Automatic Parallelization of the Perfect Benchmarks R Rudolf Eigenmanny Jay Hoeflinger David Padua Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign
open this document and view contentsftp://sp2.csrd.uiuc.edu/pub/CSRD_Reports/reports/1500.ps.gz, 19960821
THE DESIGN OF AN EFFICIENT AND PORTABLE INTERFACE BETWEEN A PARALLELIZING COMPILER AND ITS TARGET MACHINE BY JEE MYEONG KU B.S., University of Illinois, 1993 THESIS Submitted in partial fulfillment of the requirements for the degree of Master of Science in Electrical Engineering in the Graduate College
open this document and view contentsftp://sp2.csrd.uiuc.edu/pub/CSRD_Reports/reports/1501.ps.gz, 19960821
IMPLEMENTATION OF RUN TIME TECHNIQUES IN THE POLARIS FORTRAN RESTRUCTURER BY THOMAS ROBERT LAWRENCE B. A., University of Wisconsin -- Madison, 1994 THESIS Submitted in partial fulfillment of the requirements for the degree of Master of Science in Computer Science in the Graduate College of the
open this document and view contentsftp://sp2.csrd.uiuc.edu/pub/CSRD_Reports/reports/1492.ps.gz, 19961021
Compiler Support for Maintaining Cache Coherence Using Data Prefetching (Extended Abstract) Hock-Beng Lim1, Lynn Choi2 and Pen-Chung Yew3 1 Center for Supercomputing R & D, Univ. of Illinois, Urbana, IL 61801 2 Microprocessor Group, Intel Corporation, Santa Clara, CA 95095 3 Dept. of Computer Science,
open this document and view contentsftp://sp2.csrd.uiuc.edu/pub/CSRD_Reports/reports/1507.ps.gz, 19961106
Compiling for Scalable Multiprocessors with Polaris Yunheung Paek David A. Padua Department of Computer Science University of Illinois at Urbana-Champaign, 1304 West Springfield Avenue, Urbana, IL 61801, USA fpaek,paduag@csrd.uiuc.edu
open this document and view contentsftp://sp2.csrd.uiuc.edu/pub/CSRD_Reports/reports/1508.ps.gz, 19961112
Access Regions: Toward a Powerful Parallelizing Compiler Yunheung Paek, Jay Hoeflinger, David Padua Department of Computer Science University of Illinois at Urbana-Champaign, 1304 West Springfield Avenue, Urbana, IL 61801, USA fpaek,hoefling,paduag@csrd.uiuc.edu Keywords: Compilers, Aggregation,
open this document and view contentsftp://sp2.csrd.uiuc.edu/pub/CSRD_Reports/reports/1506.ps.gz, 19961113
On the Evaluation of C++ in a Parallel Programming Environment Bill Pottenger and Bruce Schatz Digital Library Initiative National Center for Supercomputing Applications University of Illinois at Urbana-Champaign 405 North Mathews, Urbana, Illinois 61801 217-244-0630, fax: 217-244-2909
open this document and view contentsftp://sp2.csrd.uiuc.edu/pub/CSRD_Reports/reports/1409.ps.gz, 19961115
Submitted to IEEE Transactions on Parallel and Distributed Systems. (CSRD Technical Report 1349.) Parallelizing While Loops for Multiprocessor Systemsy Lawrence Rauchwerger and David Padua Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign 1308 W. Main St.,
open this document and view contentsftp://sp2.csrd.uiuc.edu/pub/CSRD_Reports/reports/1497.ps.gz, 19961115
On the Solution of Recurrences in Computer Programs Bill Pottenger November 15, 1996 1 Introduction Extensive analysis of Grand Challenge codes from NCSA, codes from the SPEC CFP95 Benchmark Suite, and codes from the Perfect Club Suite, has revealed the presence of a number of loops in which recurrences
open this document and view contentsftp://sp2.csrd.uiuc.edu/pub/CSRD_Reports/reports/1510.ps.gz, 19970103
Seismic: A Hybrid C/Fortran Seismic Processing Benchmark Bill Pottenger and Rudolf Eigenmann Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign 1308 West Main Street, Urbana, Illinois 61801-2307 217-333-6578, fax: 217-244-1351 potteng@csrd.uiuc.edu Purdue
open this document and view contentsftp://sp2.csrd.uiuc.edu/pub/CSRD_Reports/reports/1511.ps.gz, 19970103
cSpace: A Parallel C++ Information Retrieval Benchmark Bill Pottenger and Bruce Schatz Digital Library Initiative National Center for Supercomputing Applications University of Illinois at Urbana-Champaign 405 North Mathews, Urbana, Illinois 61801 217-244-0630, fax: 217-244-2909 bpottenger@ncsa.uiuc.edu,
open this document and view contentsftp://sp2.csrd.uiuc.edu/pub/CSRD_Reports/reports/1512.ps.gz, 19970107
On the Automatic Parallelization of Sparse and Irregular Fortran Codes Rafael Asenjo, Eladio Gutierrez, Yuan Lin, David Padua, Bill Pottenger, Emilio Zapata Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign 1308 West Main Street, Urbana, Illinois 61801-2307