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Abstract -- The general approach have previously been to generate and optimize logic for given, fixed control architectures. For a given control program different control architectures can, however, result in very different size and speed of the implementation. In the context of silicon compilation the control unit synthesis should include an automatic choice of architecture, optimal for the particular control program in case. In this paper a range of architectures is investigated. For each architecture it is described the reasons why the architecture is good for a certain class of control programs. It is also shown that this can be explained by characteristics of a STG description of the control program. It is proposed that these characteristics together with information about available building blocks can be used as basis for an algorithm for automatic selection among a set of commonly used architectures.

I. Introduction

For wide ranges of applications a general approach to efficient VLSI architecture is based on partitioning into multiple data paths and control units (CUs). A large part of VLSI systems built today using silicon compilation is built using synchronous design styles [1]. This is motivated by the problems of building complex VLSI systems with asynchronous methods [2]. In this paper it is therefore assumed that the systems are fully synchronous.

Silicon compilation has changed the perspective of control structures and microprogramming. Soon an entire VLSI chip can be described as a program to the synthesis system, which generates the layout of the masks.

Automatic synthesis of datapaths from a program description is today possible and a whole range of solutions can be generated depending on performance constraints [3]. Certain parts of the synthesis and optimization of control logic, such as state assignment and two level logic optimization [4],[5], have been well studied. It is also possible to generate a range of multi-level logic solutions depending on performance constraints [6].

However the general approach for CU synthesis has been to generate and optimize logic for given, fixed control architectures. For a given control program different control architectures can, however, result in very different size and speed of the implementation. In the context of silicon compilation the CU synthesis should include an automatic choice of architecture, optimal for the particular control program in case and driven by performance constraints.

Our experience is that when a designer is faced with a CU design task, he usually has a fairly limited set of architectures he chooses from. The information that the designer uses to choose an architecture is knowledge about the system that should be controlled and the control program, but also characteristics of different control architectures and of the available building blocks.

Control Architecture Selection from

State Graph Characteristics

Kenny Ranerup

cathegory: Computer-Aided Design

Department of Computer Engineering, Lund University
P.O. Box 118, S-221 00 Lund, Sweden
e-mail: [email protected]