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Abstract -- Exploration of the design space in control unit design is important. In this paper methods are evaluated for exploring the design space both at architectural level and on implementation level. Methods covers mapping of control units onto different architectures and implementation of the different architectures using different logic synthesis design styles.

I. Introduction

Automatic synthesis of datapath architectures from a program description is possible today and a whole range of solutions can be generated depending on performance constraints. For control unit (CU) synthesis the first steps towards similar possibilities have been taken.

The first step in designing a CU is the choice of an architecture suitable for the particular control program in case. The architectural choice can be greatly simplified by the use of automatic algorithms for mapping a state transition graph (STG) onto several CU architectures. This enables an exploration of the architectural design space in a way not possible before. In [1] and [2] such algorithms are described.

The second step in CU design is implementation of the architectural components in an efficient way. Several implementation methods are available today e.g. PLA, multilevel logic. Accompanied with modern logic synthesis methods the design space can be explored in both area and time directions.

In this paper the combination of architectural mapping and logic synthesis will be evaluated using a set of benchmark examples that will be evaluated for different CU architectures and different logic synthesis methods.

II. Target architectures

Three CU architectures will be used in this paper. The first is the basic FSM consisting of combinational logic and a set of state registers. This architecture will be referred to as the original architecture. The two other architectures are both based on a principle of reuse of hard-

ware resources i.e. common subsequences of states.

In many CU programs it is possible to find subsequences that occur in several places in the STG. Two sequences are identical iff they produce the same output sequences for all possible input sequences. In figure 1 the state sequence a1...d1 and a2...d2 are identical.

The basic idea of a number of architectures is to somehow reuse these state sequences so that only one copy is needed in the implementation, thereby reducing the area of the CU.

Two architectures based on this idea are presented below.

STACK architecture

Subroutines in microprogrammed CUs is one example of how common subsequences can be reused. The subroutine calling mechanism can be implemented in many ways. Saving the calling state on a stack is one possibility. The traditional FSM built with a PLA and D-flip-flops can easily be extended with a subroutine mechanism by replacing the state registers with a stack of state registers (figure 2).

The return operation in this subroutine mechanism differs from the usual microprocessor type of subroutines in that it returns the FSM to the calling state, not the state after the calling state. Traversing the STG in figure 2 would therefore lead to the sequence 1,2,a,b,c,d,2,3. An extra flip-flop is therefore

Figure 1: Identical sequences found in one STG.

2 a2

8 9

3b 2 c2 d2

a1 b1 c1 d1

-/1 -/2 -/3 -/4 -/5 -/6

-/7 -/2 -/3 -/4 -/5 -/8

Comparison of Logic Synthesis Methods in

Control Unit Architecture Synthesis

Kenny Ranerup

Department of Computer Engineering

Lund University, Sweden

Jan Madsen

Center for Integrated Electronics, DTH

Lyngby, Denmark