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Using Graphics and Animation to Visualize

Instruction Pipelining and its Hazards

Per Stenstr?om, H?akan Nilsson, and Jonas Skeppstedt

Department of Computer Engineering, Lund University

P.O. Box 118, S-221 00 LUND, Sweden


The breakthrough of pipelined microprocessors has brought about a need to teach instruction pipelining in electrical and computer engineering curricula at the undergraduate level to a considerable depth. Although the idea of pipelining is conceptually simple, students often find pipelining difficult to visualize. Only the most talented students assimilate the ideas of how hazard issues are eliminated.

Based on the pedagogical approach used in the landmark book ?Computer Architecture?A Quantitative Approach? by John Hennessy and David Patterson, we have developed a graphical tool that uses animation and other graphical techniques to visualize how a pipelined datapath and control unit work. In this paper, we describe the graphical tool and outline a laboratory that makes use of it.

1 Introduction

The last decade has seen a tremendous performance improvement of microprocessors. Two factors are responsible for this improvement. First, semiconductor speed improvements have increased the performance. However, as pointed out by Hennessy and Jouppi in [3], instruction pipelining is an equally important contributor to increased performance.

Historically, instruction pipelining has been used ever since the IBM 360/91 [1] was announced back in the 60's. Almost thirty years after, we see a new generation of machines that make heavy use of instruction pipelining such as the recently announced DEC Alpha series [2]. Although pipelining is not responsible for all performance improvements?e.g. a suitable instruction set model must be identified and an efficient memory hierarchy has to be designed?it is definitely such an important contributor that engineers have to get an in-depth understanding in (i) why it works (ii) what issues it raises, and (iii) how a pipeline can be constructed. We believe that it is not possible to understand the performance limitations of contemporary microprocessors, without carefully addressing the above issues.

About two years ago, Hennessy and Patterson issued the landmark book in computer architecture [4]. It has provided students in computer architecture with a comprehensive view of the quantitative observations that have led to the breakthrough of pipelined microprocessors. It also presents how instruction pipelines work by introducing the hazard issues that all pipeline designers are faced with. This is done in a systematic fashion by starting up with a simple pipeline model based on the DLX instruction set model, and then introducingthe functionality that is needed to eliminate various hazard problems step-by-step.

We have adopted the book here in Lund as almost anybody else. Although the book is superb, students still find it difficult to understand how pipelining works and the various techniques to eliminate hazards. In our experience, it is mainly due to the lack of visualization of the parallelism inherent in pipelining. We have found that having a graphical tool that can show that parts of several instructions are executed in parallel is a key aspect of teaching all issues related to instruction pipelining.

We have developed a graphical tool that, based on the hypothetical instruction set model DLX [4], makes it possible to study the parallel actions involved in a pipelined datapath and control unit. We have also successfully developed a laboratory based on the tool that uses the same pedagogical approach as in [4]. In this paper, we report on the graphical tool and how it is used to convey the most important aspects of instruction pipelining.

In Section 2, we present the approach taken to teach instruction pipelining. In Section 3, we outline the capability of the graphical simulator and the laboratory assignments. In Section 4, we discuss the implementation of the tool, and in Section 5, we conclude the paper.

2 How Pipelining is Taught

Based on prerequisite courses in digital design and assembly language programming for the Motorola 68000 [5], the