Logic extraction from CMOS transistor

networks

Per Andersson and Kenny Ranerup,
Department of Computer Engineering,
Lund University, Sweden.

Abstract
A tool has been developed capable of analyzing a CMOS transistor network and identifying all clocked memory elements (latches, flip-flops etc). The rest of the transistor network is expressed as a set of logic equations. This kind of representation is much more efficient to use for logic verification than the traditional switch level models, and can be used both for formal methods and for simulation.
The network may have any structure and it may contain a wide range of combinational paths (static or pseudo-NMOS), precharged storage nodes, domino logic etc. A fundamental restriction is that one external, two-phase, non-overlapping clock signal is used as the primary source for all clocking. Except for static pullups, all transistors are assumed to operate as switches and asynchrounous feedbacks may exist only within memory elements.
The analysis is based on the fact that any kind of clocked memory element (such as flipflops of type D, JK etc) can be expressed as an equivalent network of clocked latches and combinational logic. If, for a particular memory element, the clock signal used in the original network has been derived from the primary clock, the corresponding logic for the clock is included in the extracted equivalent of that element.
Thus, the original transistor network is transformed to an equivalent network of standard latches and blocks of combinational logic expressed as two-level logic equations. In this network all latches are controlled by the primary clock.
During the analysis a number of transformations are used in order to eliminate redundancy and reduce the size of the final network. All loops in the network are traversed and redundant latches removed. After this step each loop will contain an even number of latches clocked alternatively by one of the two phases. Standard methods of two level logic optimization are applied to the combinational part.
Special considerations have been made in order to reduce the computational complexity. Examples of networks containing 20-100 transistors have been run so far with an execution time in the order of a few minutes on a Sun 3/50 workstation.

1 Background

The increasing complexity of VLSI designs and the tools that the designer use rises an important issue. How is it possible to guarantie that the design is correct? This problem consist of two parts. The correctness of the design and the correctness of the designtools.

The design tools are today so complex that there is no way of verifying that they always produce a correct result. If it would be possible to verify every design against the specification in a formal manner, the problem would be solved. This approach is today impossible to do automatically for realistic designs. The formal verification has been carried out partly by hand for some small designs like the SAFE processor. This verification takes several times longer than the design process and is therefore unusable for most designs.
The goal of this paper is to present a solution to a part of the verification process.